1484276119
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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bindings | ||
00-INDEX | ||
booting-without-of.txt | ||
changesets.txt | ||
dynamic-resolution-notes.txt | ||
of_selftest.txt | ||
overlay-notes.txt | ||
todo.txt | ||
usage-model.txt |