SRQ table is accessed both from interrupt and process context, therefore we must use xa_lock_irq. inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. kworker/u17:9/8573 takes: ffff8883e3503d30 (&xa->xa_lock#13){?...}-{2:2}, at: mlx5_cmd_get_srq+0x18/0x70 [mlx5_ib] {IN-HARDIRQ-W} state was registered at: lock_acquire+0xb9/0x3a0 _raw_spin_lock+0x25/0x30 srq_event_notifier+0x2b/0xc0 [mlx5_ib] notifier_call_chain+0x45/0x70 __atomic_notifier_call_chain+0x69/0x100 forward_event+0x36/0xc0 [mlx5_core] notifier_call_chain+0x45/0x70 __atomic_notifier_call_chain+0x69/0x100 mlx5_eq_async_int+0xc5/0x160 [mlx5_core] notifier_call_chain+0x45/0x70 __atomic_notifier_call_chain+0x69/0x100 mlx5_irq_int_handler+0x19/0x30 [mlx5_core] __handle_irq_event_percpu+0x43/0x2a0 handle_irq_event_percpu+0x30/0x70 handle_irq_event+0x34/0x60 handle_edge_irq+0x7c/0x1b0 do_IRQ+0x60/0x110 ret_from_intr+0x0/0x2a default_idle+0x34/0x160 do_idle+0x1ec/0x220 cpu_startup_entry+0x19/0x20 start_secondary+0x153/0x1a0 secondary_startup_64+0xa4/0xb0 irq event stamp: 20907 hardirqs last enabled at (20907): _raw_spin_unlock_irq+0x24/0x30 hardirqs last disabled at (20906): _raw_spin_lock_irq+0xf/0x40 softirqs last enabled at (20746): __do_softirq+0x2c9/0x436 softirqs last disabled at (20681): irq_exit+0xb3/0xc0 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&xa->xa_lock#13); <Interrupt> lock(&xa->xa_lock#13); *** DEADLOCK *** 2 locks held by kworker/u17:9/8573: #0: ffff888295218d38 ((wq_completion)mlx5_ib_page_fault){+.+.}-{0:0}, at: process_one_work+0x1f1/0x5f0 #1: ffff888401647e78 ((work_completion)(&pfault->work)){+.+.}-{0:0}, at: process_one_work+0x1f1/0x5f0 stack backtrace: CPU: 0 PID: 8573 Comm: kworker/u17:9 Tainted: GO 5.7.0_for_upstream_min_debug_2020_06_14_11_31_46_41 #1 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.org 04/01/2014 Workqueue: mlx5_ib_page_fault mlx5_ib_eqe_pf_action [mlx5_ib] Call Trace: dump_stack+0x71/0x9b mark_lock+0x4f2/0x590 ? print_shortest_lock_dependencies+0x200/0x200 __lock_acquire+0xa00/0x1eb0 lock_acquire+0xb9/0x3a0 ? mlx5_cmd_get_srq+0x18/0x70 [mlx5_ib] _raw_spin_lock+0x25/0x30 ? mlx5_cmd_get_srq+0x18/0x70 [mlx5_ib] mlx5_cmd_get_srq+0x18/0x70 [mlx5_ib] mlx5_ib_eqe_pf_action+0x257/0xa30 [mlx5_ib] ? process_one_work+0x209/0x5f0 process_one_work+0x27b/0x5f0 ? __schedule+0x280/0x7e0 worker_thread+0x2d/0x3c0 ? process_one_work+0x5f0/0x5f0 kthread+0x111/0x130 ? kthread_park+0x90/0x90 ret_from_fork+0x24/0x30 Fixes: e126ba97dba9 ("mlx5: Add driver for Mellanox Connect-IB adapters") Link: https://lore.kernel.org/r/20200712102641.15210-1-leon@kernel.org Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
693 lines
18 KiB
C
693 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/*
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* Copyright (c) 2013-2018, Mellanox Technologies inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/mlx5/driver.h>
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#include "mlx5_ib.h"
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#include "srq.h"
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#include "qp.h"
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static int get_pas_size(struct mlx5_srq_attr *in)
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{
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u32 log_page_size = in->log_page_size + 12;
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u32 log_srq_size = in->log_size;
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u32 log_rq_stride = in->wqe_shift;
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u32 page_offset = in->page_offset;
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u32 po_quanta = 1 << (log_page_size - 6);
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u32 rq_sz = 1 << (log_srq_size + 4 + log_rq_stride);
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u32 page_size = 1 << log_page_size;
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u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
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u32 rq_num_pas = DIV_ROUND_UP(rq_sz_po, page_size);
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return rq_num_pas * sizeof(u64);
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}
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static void set_wq(void *wq, struct mlx5_srq_attr *in)
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{
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MLX5_SET(wq, wq, wq_signature, !!(in->flags
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& MLX5_SRQ_FLAG_WQ_SIG));
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MLX5_SET(wq, wq, log_wq_pg_sz, in->log_page_size);
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MLX5_SET(wq, wq, log_wq_stride, in->wqe_shift + 4);
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MLX5_SET(wq, wq, log_wq_sz, in->log_size);
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MLX5_SET(wq, wq, page_offset, in->page_offset);
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MLX5_SET(wq, wq, lwm, in->lwm);
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MLX5_SET(wq, wq, pd, in->pd);
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MLX5_SET64(wq, wq, dbr_addr, in->db_record);
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}
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static void set_srqc(void *srqc, struct mlx5_srq_attr *in)
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{
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MLX5_SET(srqc, srqc, wq_signature, !!(in->flags
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& MLX5_SRQ_FLAG_WQ_SIG));
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MLX5_SET(srqc, srqc, log_page_size, in->log_page_size);
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MLX5_SET(srqc, srqc, log_rq_stride, in->wqe_shift);
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MLX5_SET(srqc, srqc, log_srq_size, in->log_size);
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MLX5_SET(srqc, srqc, page_offset, in->page_offset);
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MLX5_SET(srqc, srqc, lwm, in->lwm);
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MLX5_SET(srqc, srqc, pd, in->pd);
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MLX5_SET64(srqc, srqc, dbr_addr, in->db_record);
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MLX5_SET(srqc, srqc, xrcd, in->xrcd);
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MLX5_SET(srqc, srqc, cqn, in->cqn);
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}
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static void get_wq(void *wq, struct mlx5_srq_attr *in)
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{
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if (MLX5_GET(wq, wq, wq_signature))
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in->flags &= MLX5_SRQ_FLAG_WQ_SIG;
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in->log_page_size = MLX5_GET(wq, wq, log_wq_pg_sz);
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in->wqe_shift = MLX5_GET(wq, wq, log_wq_stride) - 4;
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in->log_size = MLX5_GET(wq, wq, log_wq_sz);
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in->page_offset = MLX5_GET(wq, wq, page_offset);
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in->lwm = MLX5_GET(wq, wq, lwm);
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in->pd = MLX5_GET(wq, wq, pd);
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in->db_record = MLX5_GET64(wq, wq, dbr_addr);
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}
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static void get_srqc(void *srqc, struct mlx5_srq_attr *in)
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{
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if (MLX5_GET(srqc, srqc, wq_signature))
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in->flags &= MLX5_SRQ_FLAG_WQ_SIG;
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in->log_page_size = MLX5_GET(srqc, srqc, log_page_size);
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in->wqe_shift = MLX5_GET(srqc, srqc, log_rq_stride);
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in->log_size = MLX5_GET(srqc, srqc, log_srq_size);
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in->page_offset = MLX5_GET(srqc, srqc, page_offset);
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in->lwm = MLX5_GET(srqc, srqc, lwm);
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in->pd = MLX5_GET(srqc, srqc, pd);
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in->db_record = MLX5_GET64(srqc, srqc, dbr_addr);
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}
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struct mlx5_core_srq *mlx5_cmd_get_srq(struct mlx5_ib_dev *dev, u32 srqn)
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{
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struct mlx5_srq_table *table = &dev->srq_table;
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struct mlx5_core_srq *srq;
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xa_lock_irq(&table->array);
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srq = xa_load(&table->array, srqn);
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if (srq)
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refcount_inc(&srq->common.refcount);
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xa_unlock_irq(&table->array);
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return srq;
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}
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static int create_srq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *in)
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{
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u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0};
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void *create_in;
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void *srqc;
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void *pas;
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int pas_size;
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int inlen;
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int err;
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pas_size = get_pas_size(in);
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inlen = MLX5_ST_SZ_BYTES(create_srq_in) + pas_size;
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create_in = kvzalloc(inlen, GFP_KERNEL);
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if (!create_in)
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return -ENOMEM;
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MLX5_SET(create_srq_in, create_in, uid, in->uid);
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srqc = MLX5_ADDR_OF(create_srq_in, create_in, srq_context_entry);
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pas = MLX5_ADDR_OF(create_srq_in, create_in, pas);
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set_srqc(srqc, in);
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memcpy(pas, in->pas, pas_size);
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MLX5_SET(create_srq_in, create_in, opcode,
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MLX5_CMD_OP_CREATE_SRQ);
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err = mlx5_cmd_exec(dev->mdev, create_in, inlen, create_out,
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sizeof(create_out));
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kvfree(create_in);
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if (!err) {
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srq->srqn = MLX5_GET(create_srq_out, create_out, srqn);
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srq->uid = in->uid;
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}
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return err;
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}
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static int destroy_srq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_srq_in)] = {};
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MLX5_SET(destroy_srq_in, in, opcode, MLX5_CMD_OP_DESTROY_SRQ);
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MLX5_SET(destroy_srq_in, in, srqn, srq->srqn);
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MLX5_SET(destroy_srq_in, in, uid, srq->uid);
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return mlx5_cmd_exec_in(dev->mdev, destroy_srq, in);
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}
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static int arm_srq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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u16 lwm, int is_srq)
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{
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u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {};
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MLX5_SET(arm_rq_in, in, opcode, MLX5_CMD_OP_ARM_RQ);
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MLX5_SET(arm_rq_in, in, op_mod, MLX5_ARM_RQ_IN_OP_MOD_SRQ);
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MLX5_SET(arm_rq_in, in, srq_number, srq->srqn);
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MLX5_SET(arm_rq_in, in, lwm, lwm);
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MLX5_SET(arm_rq_in, in, uid, srq->uid);
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return mlx5_cmd_exec_in(dev->mdev, arm_rq, in);
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}
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static int query_srq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *out)
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{
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u32 in[MLX5_ST_SZ_DW(query_srq_in)] = {};
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u32 *srq_out;
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void *srqc;
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int err;
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srq_out = kvzalloc(MLX5_ST_SZ_BYTES(query_srq_out), GFP_KERNEL);
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if (!srq_out)
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return -ENOMEM;
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MLX5_SET(query_srq_in, in, opcode, MLX5_CMD_OP_QUERY_SRQ);
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MLX5_SET(query_srq_in, in, srqn, srq->srqn);
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err = mlx5_cmd_exec_inout(dev->mdev, query_srq, in, srq_out);
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if (err)
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goto out;
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srqc = MLX5_ADDR_OF(query_srq_out, srq_out, srq_context_entry);
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get_srqc(srqc, out);
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if (MLX5_GET(srqc, srqc, state) != MLX5_SRQC_STATE_GOOD)
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out->flags |= MLX5_SRQ_FLAG_ERR;
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out:
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kvfree(srq_out);
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return err;
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}
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static int create_xrc_srq_cmd(struct mlx5_ib_dev *dev,
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struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *in)
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{
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u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)];
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void *create_in;
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void *xrc_srqc;
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void *pas;
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int pas_size;
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int inlen;
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int err;
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pas_size = get_pas_size(in);
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inlen = MLX5_ST_SZ_BYTES(create_xrc_srq_in) + pas_size;
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create_in = kvzalloc(inlen, GFP_KERNEL);
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if (!create_in)
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return -ENOMEM;
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MLX5_SET(create_xrc_srq_in, create_in, uid, in->uid);
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xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, create_in,
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xrc_srq_context_entry);
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pas = MLX5_ADDR_OF(create_xrc_srq_in, create_in, pas);
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set_srqc(xrc_srqc, in);
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MLX5_SET(xrc_srqc, xrc_srqc, user_index, in->user_index);
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memcpy(pas, in->pas, pas_size);
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MLX5_SET(create_xrc_srq_in, create_in, opcode,
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MLX5_CMD_OP_CREATE_XRC_SRQ);
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memset(create_out, 0, sizeof(create_out));
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err = mlx5_cmd_exec(dev->mdev, create_in, inlen, create_out,
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sizeof(create_out));
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if (err)
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goto out;
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srq->srqn = MLX5_GET(create_xrc_srq_out, create_out, xrc_srqn);
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srq->uid = in->uid;
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out:
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kvfree(create_in);
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return err;
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}
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static int destroy_xrc_srq_cmd(struct mlx5_ib_dev *dev,
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struct mlx5_core_srq *srq)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {};
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MLX5_SET(destroy_xrc_srq_in, in, opcode, MLX5_CMD_OP_DESTROY_XRC_SRQ);
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MLX5_SET(destroy_xrc_srq_in, in, xrc_srqn, srq->srqn);
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MLX5_SET(destroy_xrc_srq_in, in, uid, srq->uid);
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return mlx5_cmd_exec_in(dev->mdev, destroy_xrc_srq, in);
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}
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static int arm_xrc_srq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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u16 lwm)
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{
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u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {};
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MLX5_SET(arm_xrc_srq_in, in, opcode, MLX5_CMD_OP_ARM_XRC_SRQ);
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MLX5_SET(arm_xrc_srq_in, in, op_mod,
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MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ);
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MLX5_SET(arm_xrc_srq_in, in, xrc_srqn, srq->srqn);
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MLX5_SET(arm_xrc_srq_in, in, lwm, lwm);
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MLX5_SET(arm_xrc_srq_in, in, uid, srq->uid);
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return mlx5_cmd_exec_in(dev->mdev, arm_xrc_srq, in);
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}
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static int query_xrc_srq_cmd(struct mlx5_ib_dev *dev,
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struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *out)
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{
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u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {};
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u32 *xrcsrq_out;
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void *xrc_srqc;
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int err;
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xrcsrq_out = kvzalloc(MLX5_ST_SZ_BYTES(query_xrc_srq_out), GFP_KERNEL);
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if (!xrcsrq_out)
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return -ENOMEM;
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MLX5_SET(query_xrc_srq_in, in, opcode, MLX5_CMD_OP_QUERY_XRC_SRQ);
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MLX5_SET(query_xrc_srq_in, in, xrc_srqn, srq->srqn);
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err = mlx5_cmd_exec_inout(dev->mdev, query_xrc_srq, in, xrcsrq_out);
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if (err)
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goto out;
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xrc_srqc = MLX5_ADDR_OF(query_xrc_srq_out, xrcsrq_out,
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xrc_srq_context_entry);
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get_srqc(xrc_srqc, out);
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if (MLX5_GET(xrc_srqc, xrc_srqc, state) != MLX5_XRC_SRQC_STATE_GOOD)
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out->flags |= MLX5_SRQ_FLAG_ERR;
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out:
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kvfree(xrcsrq_out);
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return err;
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}
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static int create_rmp_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *in)
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{
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void *create_out = NULL;
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void *create_in = NULL;
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void *rmpc;
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void *wq;
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int pas_size;
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int outlen;
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int inlen;
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int err;
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pas_size = get_pas_size(in);
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inlen = MLX5_ST_SZ_BYTES(create_rmp_in) + pas_size;
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outlen = MLX5_ST_SZ_BYTES(create_rmp_out);
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create_in = kvzalloc(inlen, GFP_KERNEL);
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create_out = kvzalloc(outlen, GFP_KERNEL);
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if (!create_in || !create_out) {
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err = -ENOMEM;
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goto out;
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}
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rmpc = MLX5_ADDR_OF(create_rmp_in, create_in, ctx);
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wq = MLX5_ADDR_OF(rmpc, rmpc, wq);
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MLX5_SET(rmpc, rmpc, state, MLX5_RMPC_STATE_RDY);
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MLX5_SET(create_rmp_in, create_in, uid, in->uid);
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set_wq(wq, in);
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memcpy(MLX5_ADDR_OF(rmpc, rmpc, wq.pas), in->pas, pas_size);
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MLX5_SET(create_rmp_in, create_in, opcode, MLX5_CMD_OP_CREATE_RMP);
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err = mlx5_cmd_exec(dev->mdev, create_in, inlen, create_out, outlen);
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if (!err) {
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srq->srqn = MLX5_GET(create_rmp_out, create_out, rmpn);
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srq->uid = in->uid;
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}
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out:
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kvfree(create_in);
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kvfree(create_out);
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return err;
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}
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static int destroy_rmp_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {};
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MLX5_SET(destroy_rmp_in, in, opcode, MLX5_CMD_OP_DESTROY_RMP);
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MLX5_SET(destroy_rmp_in, in, rmpn, srq->srqn);
|
|
MLX5_SET(destroy_rmp_in, in, uid, srq->uid);
|
|
return mlx5_cmd_exec_in(dev->mdev, destroy_rmp, in);
|
|
}
|
|
|
|
static int arm_rmp_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
u16 lwm)
|
|
{
|
|
void *out = NULL;
|
|
void *in = NULL;
|
|
void *rmpc;
|
|
void *wq;
|
|
void *bitmask;
|
|
int outlen;
|
|
int inlen;
|
|
int err;
|
|
|
|
inlen = MLX5_ST_SZ_BYTES(modify_rmp_in);
|
|
outlen = MLX5_ST_SZ_BYTES(modify_rmp_out);
|
|
|
|
in = kvzalloc(inlen, GFP_KERNEL);
|
|
out = kvzalloc(outlen, GFP_KERNEL);
|
|
if (!in || !out) {
|
|
err = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
rmpc = MLX5_ADDR_OF(modify_rmp_in, in, ctx);
|
|
bitmask = MLX5_ADDR_OF(modify_rmp_in, in, bitmask);
|
|
wq = MLX5_ADDR_OF(rmpc, rmpc, wq);
|
|
|
|
MLX5_SET(modify_rmp_in, in, rmp_state, MLX5_RMPC_STATE_RDY);
|
|
MLX5_SET(modify_rmp_in, in, rmpn, srq->srqn);
|
|
MLX5_SET(modify_rmp_in, in, uid, srq->uid);
|
|
MLX5_SET(wq, wq, lwm, lwm);
|
|
MLX5_SET(rmp_bitmask, bitmask, lwm, 1);
|
|
MLX5_SET(rmpc, rmpc, state, MLX5_RMPC_STATE_RDY);
|
|
MLX5_SET(modify_rmp_in, in, opcode, MLX5_CMD_OP_MODIFY_RMP);
|
|
|
|
err = mlx5_cmd_exec_inout(dev->mdev, modify_rmp, in, out);
|
|
|
|
out:
|
|
kvfree(in);
|
|
kvfree(out);
|
|
return err;
|
|
}
|
|
|
|
static int query_rmp_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *out)
|
|
{
|
|
u32 *rmp_out = NULL;
|
|
u32 *rmp_in = NULL;
|
|
void *rmpc;
|
|
int outlen;
|
|
int inlen;
|
|
int err;
|
|
|
|
outlen = MLX5_ST_SZ_BYTES(query_rmp_out);
|
|
inlen = MLX5_ST_SZ_BYTES(query_rmp_in);
|
|
|
|
rmp_out = kvzalloc(outlen, GFP_KERNEL);
|
|
rmp_in = kvzalloc(inlen, GFP_KERNEL);
|
|
if (!rmp_out || !rmp_in) {
|
|
err = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
MLX5_SET(query_rmp_in, rmp_in, opcode, MLX5_CMD_OP_QUERY_RMP);
|
|
MLX5_SET(query_rmp_in, rmp_in, rmpn, srq->srqn);
|
|
err = mlx5_cmd_exec_inout(dev->mdev, query_rmp, rmp_in, rmp_out);
|
|
if (err)
|
|
goto out;
|
|
|
|
rmpc = MLX5_ADDR_OF(query_rmp_out, rmp_out, rmp_context);
|
|
get_wq(MLX5_ADDR_OF(rmpc, rmpc, wq), out);
|
|
if (MLX5_GET(rmpc, rmpc, state) != MLX5_RMPC_STATE_RDY)
|
|
out->flags |= MLX5_SRQ_FLAG_ERR;
|
|
|
|
out:
|
|
kvfree(rmp_out);
|
|
kvfree(rmp_in);
|
|
return err;
|
|
}
|
|
|
|
static int create_xrq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *in)
|
|
{
|
|
u32 create_out[MLX5_ST_SZ_DW(create_xrq_out)] = {0};
|
|
void *create_in;
|
|
void *xrqc;
|
|
void *wq;
|
|
int pas_size;
|
|
int inlen;
|
|
int err;
|
|
|
|
pas_size = get_pas_size(in);
|
|
inlen = MLX5_ST_SZ_BYTES(create_xrq_in) + pas_size;
|
|
create_in = kvzalloc(inlen, GFP_KERNEL);
|
|
if (!create_in)
|
|
return -ENOMEM;
|
|
|
|
xrqc = MLX5_ADDR_OF(create_xrq_in, create_in, xrq_context);
|
|
wq = MLX5_ADDR_OF(xrqc, xrqc, wq);
|
|
|
|
set_wq(wq, in);
|
|
memcpy(MLX5_ADDR_OF(xrqc, xrqc, wq.pas), in->pas, pas_size);
|
|
|
|
if (in->type == IB_SRQT_TM) {
|
|
MLX5_SET(xrqc, xrqc, topology, MLX5_XRQC_TOPOLOGY_TAG_MATCHING);
|
|
if (in->flags & MLX5_SRQ_FLAG_RNDV)
|
|
MLX5_SET(xrqc, xrqc, offload, MLX5_XRQC_OFFLOAD_RNDV);
|
|
MLX5_SET(xrqc, xrqc,
|
|
tag_matching_topology_context.log_matching_list_sz,
|
|
in->tm_log_list_size);
|
|
}
|
|
MLX5_SET(xrqc, xrqc, user_index, in->user_index);
|
|
MLX5_SET(xrqc, xrqc, cqn, in->cqn);
|
|
MLX5_SET(create_xrq_in, create_in, opcode, MLX5_CMD_OP_CREATE_XRQ);
|
|
MLX5_SET(create_xrq_in, create_in, uid, in->uid);
|
|
err = mlx5_cmd_exec(dev->mdev, create_in, inlen, create_out,
|
|
sizeof(create_out));
|
|
kvfree(create_in);
|
|
if (!err) {
|
|
srq->srqn = MLX5_GET(create_xrq_out, create_out, xrqn);
|
|
srq->uid = in->uid;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int destroy_xrq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(destroy_xrq_in)] = {};
|
|
|
|
MLX5_SET(destroy_xrq_in, in, opcode, MLX5_CMD_OP_DESTROY_XRQ);
|
|
MLX5_SET(destroy_xrq_in, in, xrqn, srq->srqn);
|
|
MLX5_SET(destroy_xrq_in, in, uid, srq->uid);
|
|
|
|
return mlx5_cmd_exec_in(dev->mdev, destroy_xrq, in);
|
|
}
|
|
|
|
static int arm_xrq_cmd(struct mlx5_ib_dev *dev,
|
|
struct mlx5_core_srq *srq,
|
|
u16 lwm)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {};
|
|
|
|
MLX5_SET(arm_rq_in, in, opcode, MLX5_CMD_OP_ARM_RQ);
|
|
MLX5_SET(arm_rq_in, in, op_mod, MLX5_ARM_RQ_IN_OP_MOD_XRQ);
|
|
MLX5_SET(arm_rq_in, in, srq_number, srq->srqn);
|
|
MLX5_SET(arm_rq_in, in, lwm, lwm);
|
|
MLX5_SET(arm_rq_in, in, uid, srq->uid);
|
|
|
|
return mlx5_cmd_exec_in(dev->mdev, arm_rq, in);
|
|
}
|
|
|
|
static int query_xrq_cmd(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *out)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(query_xrq_in)] = {};
|
|
u32 *xrq_out;
|
|
int outlen = MLX5_ST_SZ_BYTES(query_xrq_out);
|
|
void *xrqc;
|
|
int err;
|
|
|
|
xrq_out = kvzalloc(outlen, GFP_KERNEL);
|
|
if (!xrq_out)
|
|
return -ENOMEM;
|
|
|
|
MLX5_SET(query_xrq_in, in, opcode, MLX5_CMD_OP_QUERY_XRQ);
|
|
MLX5_SET(query_xrq_in, in, xrqn, srq->srqn);
|
|
|
|
err = mlx5_cmd_exec_inout(dev->mdev, query_xrq, in, xrq_out);
|
|
if (err)
|
|
goto out;
|
|
|
|
xrqc = MLX5_ADDR_OF(query_xrq_out, xrq_out, xrq_context);
|
|
get_wq(MLX5_ADDR_OF(xrqc, xrqc, wq), out);
|
|
if (MLX5_GET(xrqc, xrqc, state) != MLX5_XRQC_STATE_GOOD)
|
|
out->flags |= MLX5_SRQ_FLAG_ERR;
|
|
out->tm_next_tag =
|
|
MLX5_GET(xrqc, xrqc,
|
|
tag_matching_topology_context.append_next_index);
|
|
out->tm_hw_phase_cnt =
|
|
MLX5_GET(xrqc, xrqc,
|
|
tag_matching_topology_context.hw_phase_cnt);
|
|
out->tm_sw_phase_cnt =
|
|
MLX5_GET(xrqc, xrqc,
|
|
tag_matching_topology_context.sw_phase_cnt);
|
|
|
|
out:
|
|
kvfree(xrq_out);
|
|
return err;
|
|
}
|
|
|
|
static int create_srq_split(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *in)
|
|
{
|
|
if (!dev->mdev->issi)
|
|
return create_srq_cmd(dev, srq, in);
|
|
switch (srq->common.res) {
|
|
case MLX5_RES_XSRQ:
|
|
return create_xrc_srq_cmd(dev, srq, in);
|
|
case MLX5_RES_XRQ:
|
|
return create_xrq_cmd(dev, srq, in);
|
|
default:
|
|
return create_rmp_cmd(dev, srq, in);
|
|
}
|
|
}
|
|
|
|
static int destroy_srq_split(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq)
|
|
{
|
|
if (!dev->mdev->issi)
|
|
return destroy_srq_cmd(dev, srq);
|
|
switch (srq->common.res) {
|
|
case MLX5_RES_XSRQ:
|
|
return destroy_xrc_srq_cmd(dev, srq);
|
|
case MLX5_RES_XRQ:
|
|
return destroy_xrq_cmd(dev, srq);
|
|
default:
|
|
return destroy_rmp_cmd(dev, srq);
|
|
}
|
|
}
|
|
|
|
int mlx5_cmd_create_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *in)
|
|
{
|
|
struct mlx5_srq_table *table = &dev->srq_table;
|
|
int err;
|
|
|
|
switch (in->type) {
|
|
case IB_SRQT_XRC:
|
|
srq->common.res = MLX5_RES_XSRQ;
|
|
break;
|
|
case IB_SRQT_TM:
|
|
srq->common.res = MLX5_RES_XRQ;
|
|
break;
|
|
default:
|
|
srq->common.res = MLX5_RES_SRQ;
|
|
}
|
|
|
|
err = create_srq_split(dev, srq, in);
|
|
if (err)
|
|
return err;
|
|
|
|
refcount_set(&srq->common.refcount, 1);
|
|
init_completion(&srq->common.free);
|
|
|
|
err = xa_err(xa_store_irq(&table->array, srq->srqn, srq, GFP_KERNEL));
|
|
if (err)
|
|
goto err_destroy_srq_split;
|
|
|
|
return 0;
|
|
|
|
err_destroy_srq_split:
|
|
destroy_srq_split(dev, srq);
|
|
|
|
return err;
|
|
}
|
|
|
|
void mlx5_cmd_destroy_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq)
|
|
{
|
|
struct mlx5_srq_table *table = &dev->srq_table;
|
|
struct mlx5_core_srq *tmp;
|
|
int err;
|
|
|
|
tmp = xa_erase_irq(&table->array, srq->srqn);
|
|
if (!tmp || tmp != srq)
|
|
return;
|
|
|
|
err = destroy_srq_split(dev, srq);
|
|
if (err)
|
|
return;
|
|
|
|
mlx5_core_res_put(&srq->common);
|
|
wait_for_completion(&srq->common.free);
|
|
}
|
|
|
|
int mlx5_cmd_query_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *out)
|
|
{
|
|
if (!dev->mdev->issi)
|
|
return query_srq_cmd(dev, srq, out);
|
|
switch (srq->common.res) {
|
|
case MLX5_RES_XSRQ:
|
|
return query_xrc_srq_cmd(dev, srq, out);
|
|
case MLX5_RES_XRQ:
|
|
return query_xrq_cmd(dev, srq, out);
|
|
default:
|
|
return query_rmp_cmd(dev, srq, out);
|
|
}
|
|
}
|
|
|
|
int mlx5_cmd_arm_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
|
|
u16 lwm, int is_srq)
|
|
{
|
|
if (!dev->mdev->issi)
|
|
return arm_srq_cmd(dev, srq, lwm, is_srq);
|
|
switch (srq->common.res) {
|
|
case MLX5_RES_XSRQ:
|
|
return arm_xrc_srq_cmd(dev, srq, lwm);
|
|
case MLX5_RES_XRQ:
|
|
return arm_xrq_cmd(dev, srq, lwm);
|
|
default:
|
|
return arm_rmp_cmd(dev, srq, lwm);
|
|
}
|
|
}
|
|
|
|
static int srq_event_notifier(struct notifier_block *nb,
|
|
unsigned long type, void *data)
|
|
{
|
|
struct mlx5_srq_table *table;
|
|
struct mlx5_core_srq *srq;
|
|
struct mlx5_eqe *eqe;
|
|
u32 srqn;
|
|
|
|
if (type != MLX5_EVENT_TYPE_SRQ_CATAS_ERROR &&
|
|
type != MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)
|
|
return NOTIFY_DONE;
|
|
|
|
table = container_of(nb, struct mlx5_srq_table, nb);
|
|
|
|
eqe = data;
|
|
srqn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
|
|
|
|
xa_lock(&table->array);
|
|
srq = xa_load(&table->array, srqn);
|
|
if (srq)
|
|
refcount_inc(&srq->common.refcount);
|
|
xa_unlock(&table->array);
|
|
|
|
if (!srq)
|
|
return NOTIFY_OK;
|
|
|
|
srq->event(srq, eqe->type);
|
|
|
|
mlx5_core_res_put(&srq->common);
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
int mlx5_init_srq_table(struct mlx5_ib_dev *dev)
|
|
{
|
|
struct mlx5_srq_table *table = &dev->srq_table;
|
|
|
|
memset(table, 0, sizeof(*table));
|
|
xa_init_flags(&table->array, XA_FLAGS_LOCK_IRQ);
|
|
|
|
table->nb.notifier_call = srq_event_notifier;
|
|
mlx5_notifier_register(dev->mdev, &table->nb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mlx5_cleanup_srq_table(struct mlx5_ib_dev *dev)
|
|
{
|
|
struct mlx5_srq_table *table = &dev->srq_table;
|
|
|
|
mlx5_notifier_unregister(dev->mdev, &table->nb);
|
|
}
|