90ddb3f034
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmP2dbsUHGJoZWxnYWFz
QGdvb2dsZS5jb20ACgkQWYigwDrT+vzBDg//aW2IeJYku5ENXwwnCQjBlyjBGOOZ
456KGpFt/ky0N9Jp0ZS3nQSa5YN7q+L8XY48gu6I7s1hXly8iLZKLrJN++S//k55
BadXu7mDUyVoY74LYvBe0nlXuwJul2qnq9IJLufRucrn1yoyqApAh39IRdCzi4U8
mP+wad7sQA0Si4bpf80uwn6Yq8SrDoO0mtmO/dZSXJooM2t2SnDXEL/fxMwTNDA4
XsVSP9FrbPmcTLo8mkDa8Dy7JKbL6KQJF9yDlmYzuA2spQpTf+YLLfsNnmE+850h
WTtfCjVaYtlik7i9qTB+VcN1CsGVepYKK3H5the16Aeql2Fu+Ji5KSt74C220Yi9
ZSDA93d/EfGc5egKyBdUUMFgqhe46srRUAoWcMrx2T4ARGuOm5EYCa9C8C7dFmO0
j6f9MYL3j2Sw3FROEKViRVOFfbIfVW1TXIo3x0fE0ud3xkg73eKp/++X8QeTMjox
2ArY2AWPNQpUI1oMlKxlSEd5XjFf7n/hHDtFqj9bIuJzt0/8wXQf0jCYTjhpGkRB
pmO+lColK6lp+bg8aWRRkiwN73xGdQhKaeXLo0Iq4T6xr0Lb3XoskHZvt6NIGe/A
ds5/uwtErq6kCf2G9YG1xfh+G1bimbjWwsHCNfSNXzTsWGDFTCb8tvqF90m+7+yl
bllxTXA6PO312Tw=
=/y4d
-----END PGP SIGNATURE-----
Merge tag 'pci-v6.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Rework portdrv shutdown so it disables interrupts but doesn't
disable bus mastering, which leads to hangs on Loongson LS7A
- Add mechanism to prevent Max_Read_Request_Size (MRRS) increases,
again to avoid hardware issues on Loongson LS7A (and likely other
devices based on DesignWare IP)
- Ignore devices with a firmware (DT or ACPI) node that says the
device is disabled
Resource management:
- Distribute spare resources to unconfigured hotplug bridges at
boot-time (not just when hot-adding such a bridge), which makes
hot-adding devices to docks work better. Tried this in v6.1 but had
to revert for regressions, so try again
- Fix root bus issue that dropped resources that happened to end
at 0, e.g., [bus 00]
PCI device hotplug:
- Remove device locking when marking device as disconnected so this
doesn't have to wait for concurrent driver bind/unbind to complete
- Quirk more Qualcomm bridges that don't fully implement the PCIe
Slot Status 'Command Completed' bit
Power management:
- Account for _S0W of the target bridge in acpi_pci_bridge_d3() so we
don't miss hot-add notifications for USB4 docks, Thunderbolt, etc
Reset:
- Observe delay after reset, e.g., resuming from system sleep,
regardless of whether a bridge can suspend to D3cold at runtime
- Wait for secondary bus to become ready after a bridge reset
Virtualization:
- Avoid FLR on some AMD FCH AHCI adapters where it doesn't work
- Allow independent IOMMU groups for some Wangxun NICs that prevent
peer-to-peer transactions but don't advertise an ACS Capability
Error handling:
- Configure End-to-End-CRC (ECRC) only if Linux owns the AER
Capability
- Remove redundant Device Control Error Reporting Enable in the AER
service driver since this is already done for all devices during
enumeration
ASPM:
- Add pci_enable_link_state() interface to allow drivers to enable
ASPM link state
Endpoint framework:
- Move dra7xx and tegra194 linkup processing from hard IRQ to
threaded IRQ handler
- Add a separate lock for endpoint controller list of endpoint
function drivers to prevent deadlock in callbacks
- Pass events from endpoint controller to endpoint function drivers
via callbacks instead of notifiers
Synopsys DesignWare eDMA controller driver (acked by Vinod):
- Fix CPU vs PCI address issues
- Fix source vs destination address issues
- Fix issues with interleaved transfer semantics
- Fix channel count initialization issue (issue still exists in
several other drivers)
- Clean up and improve debugfs usage so it will work on platforms
with several eDMA devices
Baikal T-1 PCIe controller driver:
- Set a 64-bit DMA mask
Freescale i.MX6 PCIe controller driver:
- Add i.MX8MM, i.MX8MQ, i.MX8MP endpoint mode DT binding and driver
support
Intel VMD host bridge driver:
- Add quirk to configure PCIe ASPM and LTR. This is normally done by
BIOS, and will be for future products
Marvell MVEBU PCIe controller driver:
- Mark this driver as broken in Kconfig since bugs prevent its daily
usage
MediaTek MT7621 PCIe controller driver:
- Delay PHY port initialization to improve boot reliability for ZBT
WE1326, ZBT WF3526-P, and some Netgear models
Qualcomm PCIe controller driver:
- Add MSM8998 DT compatible string
- Unify MSM8996 and MSM8998 clock orderings
- Add SM8350 DT binding and driver support
- Add IPQ8074 Gen3 DT binding and driver support
- Correct qcom,perst-regs in DT binding
- Add qcom_pcie_host_deinit() so the PHY is powered off and
regulators and clocks are disabled on late host-init errors
Socionext UniPhier Pro5 controller driver:
- Clean up uniphier-ep reg, clocks, resets, and their names in DT
binding
Synopsys DesignWare PCIe controller driver:
- Restrict coherent DMA mask to 32 bits for MSI, but allow controller
drivers to set 64-bit streaming DMA mask
- Add eDMA engine support in both Root Port and Endpoint controllers
Miscellaneous:
- Remove MODULE_LICENSE from boolean drivers so they don't look like
modules so modprobe can complain about them"
* tag 'pci-v6.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (86 commits)
PCI: dwc: Add Root Port and Endpoint controller eDMA engine support
PCI: bt1: Set 64-bit DMA mask
PCI: dwc: Restrict only coherent DMA mask for MSI address allocation
dmaengine: dw-edma: Prepare dw_edma_probe() for builtin callers
dmaengine: dw-edma: Depend on DW_EDMA instead of selecting it
dmaengine: dw-edma: Add mem-mapped LL-entries support
PCI: Remove MODULE_LICENSE so boolean drivers don't look like modules
PCI: hv: Drop duplicate PCI_MSI dependency
PCI/P2PDMA: Annotate RCU dereference
PCI/sysfs: Constify struct kobj_type pci_slot_ktype
PCI: hotplug: Allow marking devices as disconnected during bind/unbind
PCI: pciehp: Add Qualcomm quirk for Command Completed erratum
PCI: qcom: Add IPQ8074 Gen3 port support
dt-bindings: PCI: qcom: Add IPQ8074 Gen3 port
dt-bindings: PCI: qcom: Sort compatibles alphabetically
PCI: qcom: Fix host-init error handling
PCI: qcom: Add SM8350 support
dt-bindings: PCI: qcom: Add SM8350
dt-bindings: PCI: qcom-ep: Correct qcom,perst-regs
dt-bindings: PCI: qcom: Unify MSM8996 and MSM8998 clock order
...
418 lines
13 KiB
Plaintext
418 lines
13 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menu "DesignWare PCI Core Support"
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depends on PCI
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config PCIE_DW
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bool
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config PCIE_DW_HOST
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bool
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select PCIE_DW
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config PCIE_DW_EP
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bool
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select PCIE_DW
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config PCI_DRA7XX
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tristate
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config PCI_DRA7XX_HOST
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tristate "TI DRA7xx PCIe controller Host Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on OF && HAS_IOMEM && TI_PIPE3
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCI_DRA7XX
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default y if SOC_DRA7XX
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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host mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCI_DRA7XX_EP
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tristate "TI DRA7xx PCIe controller Endpoint Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on OF && HAS_IOMEM && TI_PIPE3
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_DRA7XX
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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endpoint mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCIE_DW_PLAT
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bool
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config PCIE_DW_PLAT_HOST
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bool "Platform bus based DesignWare PCIe Controller - Host mode"
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in host mode. There are two instances of PCIe controller in
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Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCIE_DW_PLAT_EP
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bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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depends on PCI && PCI_MSI
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in endpoint mode. There are two instances of PCIe controller
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in Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCI_EXYNOS
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tristate "Samsung Exynos PCIe controller"
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depends on ARCH_EXYNOS || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Enables support for the PCIe controller in the Samsung Exynos SoCs
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to work in host mode. The PCI controller is based on the DesignWare
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hardware and therefore the driver re-uses the DesignWare core
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functions to implement the driver.
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config PCI_IMX6
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bool
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config PCI_IMX6_HOST
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bool "Freescale i.MX6/7/8 PCIe controller host mode"
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depends on ARCH_MXC || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCI_IMX6
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help
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Enables support for the PCIe controller in the i.MX SoCs to
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work in Root Complex mode. The PCI controller on i.MX is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_IMX6_EP
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bool "Freescale i.MX6/7/8 PCIe controller endpoint mode"
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depends on ARCH_MXC || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_IMX6
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help
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Enables support for the PCIe controller in the i.MX SoCs to
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work in endpoint mode. The PCI controller on i.MX is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCIE_SPEAR13XX
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bool "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCI_KEYSTONE
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bool
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config PCI_KEYSTONE_HOST
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bool "PCI Keystone Host Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCI_KEYSTONE
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in host mode. The PCI controller on Keystone is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_KEYSTONE_EP
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bool "PCI Keystone Endpoint Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_KEYSTONE
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in endpoint mode. The PCI controller on Keystone is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller - Host mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_MSI
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select PCIE_DW_HOST
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select MFD_SYSCON
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Host mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_LAYERSCAPE_EP
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bool "Freescale Layerscape PCIe controller - Endpoint mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Endpoint mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_HISI
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe controller support on HiSilicon
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Hip05 and Hip06 SoCs
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config PCIE_QCOM
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bool "Qualcomm PCIe controller"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_MSI
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select PCIE_DW_HOST
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select CRC8
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help
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Say Y here to enable PCIe controller support on Qualcomm SoCs. The
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PCIe controller uses the DesignWare core plus Qualcomm-specific
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hardware wrappers.
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config PCIE_QCOM_EP
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tristate "Qualcomm PCIe controller - Endpoint mode"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here to enable support for the PCIe controllers on Qualcomm SoCs
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to work in endpoint mode. The PCIe controller uses the DesignWare core
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plus Qualcomm-specific hardware wrappers.
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config PCIE_ARMADA_8K
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bool "Marvell Armada-8K PCIe controller"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCIe controller support on
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Armada-8K SoCs. The PCIe controller on Armada-8K is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCIE_ARTPEC6
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bool
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config PCIE_ARTPEC6_HOST
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bool "Axis ARTPEC-6 PCIe controller Host Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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host mode. This uses the DesignWare core.
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config PCIE_ARTPEC6_EP
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bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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endpoint mode. This uses the DesignWare core.
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config PCIE_BT1
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tristate "Baikal-T1 PCIe controller"
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depends on MIPS_BAIKAL_T1 || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Enables support for the PCIe controller in the Baikal-T1 SoC to work
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in host mode. It's based on the Synopsys DWC PCIe v4.60a IP-core.
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config PCIE_ROCKCHIP_DW_HOST
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bool "Rockchip DesignWare PCIe controller"
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select PCIE_DW
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select PCIE_DW_HOST
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depends on PCI_MSI
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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depends on OF
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help
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Enables support for the DesignWare PCIe controller in the
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Rockchip SoC except RK3399.
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config PCIE_INTEL_GW
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bool "Intel Gateway PCIe host controller support"
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depends on OF && (X86 || COMPILE_TEST)
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say 'Y' here to enable PCIe Host controller support on Intel
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Gateway SoCs.
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The PCIe controller uses the DesignWare core plus Intel-specific
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hardware wrappers.
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config PCIE_KEEMBAY
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bool
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config PCIE_KEEMBAY_HOST
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bool "Intel Keem Bay PCIe controller - Host mode"
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depends on ARCH_KEEMBAY || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCIE_KEEMBAY
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help
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Say 'Y' here to enable support for the PCIe controller in Keem Bay
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to work in host mode.
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The PCIe controller is based on DesignWare Hardware and uses
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DesignWare core functions.
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config PCIE_KEEMBAY_EP
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bool "Intel Keem Bay PCIe controller - Endpoint mode"
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depends on ARCH_KEEMBAY || COMPILE_TEST
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depends on PCI_MSI
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_KEEMBAY
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help
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Say 'Y' here to enable support for the PCIe controller in Keem Bay
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to work in endpoint mode.
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The PCIe controller is based on DesignWare Hardware and uses
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DesignWare core functions.
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config PCIE_KIRIN
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depends on OF && (ARM64 || COMPILE_TEST)
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tristate "HiSilicon Kirin series SoCs PCIe controllers"
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support
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on HiSilicon Kirin series SoCs.
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config PCIE_HISI_STB
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bool "HiSilicon STB SoCs PCIe controllers"
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depends on ARCH_HISI || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on HiSilicon STB SoCs
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config PCI_MESON
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tristate "MESON PCIe controller"
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default m if ARCH_MESON
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCI controller support on Amlogic
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SoCs. The PCI controller on Amlogic is based on DesignWare hardware
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and therefore the driver re-uses the DesignWare core functions to
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implement the driver.
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config PCIE_TEGRA194
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tristate
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config PCIE_TEGRA194_HOST
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tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode"
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depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PHY_TEGRA194_P2U
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select PCIE_TEGRA194
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help
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Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to
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work in host mode. There are two instances of PCIe controllers in
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Tegra194. This controller can work either as EP or RC. In order to
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enable host-specific features PCIE_TEGRA194_HOST must be selected and
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in order to enable device-specific features PCIE_TEGRA194_EP must be
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selected. This uses the DesignWare core.
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config PCIE_TEGRA194_EP
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tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode"
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depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PHY_TEGRA194_P2U
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select PCIE_TEGRA194
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help
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Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to
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work in endpoint mode. There are two instances of PCIe controllers in
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Tegra194. This controller can work either as EP or RC. In order to
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enable host-specific features PCIE_TEGRA194_HOST must be selected and
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in order to enable device-specific features PCIE_TEGRA194_EP must be
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selected. This uses the DesignWare core.
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config PCIE_VISCONTI_HOST
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bool "Toshiba Visconti PCIe controllers"
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depends on ARCH_VISCONTI || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
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This driver supports TMPV7708 SoC.
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config PCIE_UNIPHIER
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bool "Socionext UniPhier PCIe host controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe host controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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config PCIE_UNIPHIER_EP
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bool "Socionext UniPhier PCIe endpoint controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
|
|
Say Y here if you want PCIe endpoint controller support on
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UniPhier SoCs. This driver supports Pro5 SoC.
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config PCIE_AL
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bool "Amazon Annapurna Labs PCIe controller"
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depends on OF && (ARM64 || COMPILE_TEST)
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depends on PCI_MSI
|
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select PCIE_DW_HOST
|
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select PCI_ECAM
|
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help
|
|
Say Y here to enable support of the Amazon's Annapurna Labs PCIe
|
|
controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
|
|
core plus Annapurna Labs proprietary hardware wrappers. This is
|
|
required only for DT-based platforms. ACPI platforms with the
|
|
Annapurna Labs PCIe controller don't need to enable this.
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|
|
config PCIE_FU740
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bool "SiFive FU740 PCIe host controller"
|
|
depends on PCI_MSI
|
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depends on SOC_SIFIVE || COMPILE_TEST
|
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select PCIE_DW_HOST
|
|
help
|
|
Say Y here if you want PCIe controller support for the SiFive
|
|
FU740.
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endmenu
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