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This patch updates the PCI power save handling
code, fixing ASPM hangs and handling device state D3
properly.
The WAR register is programmed with the correct
values now.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
15ae733b25