0499220d6d
DT properties which can have multiple entries need to specify what the entries are and define how many entries there can be. In the case of only a single entry, just 'maxItems: 1' is sufficient. Add the missing entry constraints. These were found with a modified meta-schema. Unfortunately, there are a few cases where the size constraints are not defined such as common bindings, so the meta-schema can't be part of the normal checks. Cc: Jens Axboe <axboe@kernel.dk> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Sebastian Reichel <sre@kernel.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sre@kernel.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Suman Anna <s-anna@ti.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210104230253.2805217-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
78 lines
1.6 KiB
YAML
78 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier PCIe PHY
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description: |
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This describes the devicetree bindings for PHY interface built into
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PCIe controller implemented on Socionext UniPhier SoCs.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro5-pcie-phy
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- socionext,uniphier-ld20-pcie-phy
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- socionext,uniphier-pxs3-pcie-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for others
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for others
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socionext,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to system control to set configurations for phy
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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pcie_phy: phy@66038000 {
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compatible = "socionext,uniphier-ld20-pcie-phy";
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reg = <0x66038000 0x4000>;
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#phy-cells = <0>;
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clock-names = "link";
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clocks = <&sys_clk 24>;
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reset-names = "link";
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resets = <&sys_rst 24>;
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socionext,syscon = <&soc_glue>;
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};
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