163d2089d2
The SST driver is the missing piece in our driver stack not upstreamed, so push it now :) This driver currently supports PCI device on Merrifield. Future updates will bring support for ACPI device as well as future update to PCI devices as well In subsequent patches support is added for DSP loading using memcpy, pcm operations and compressed ops. Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
113 lines
2.5 KiB
C
113 lines
2.5 KiB
C
/*
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* platform_sst_audio.h: sst audio platform data header file
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*
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* Copyright (C) 2012-14 Intel Corporation
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
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* Vinod Koul ,vinod.koul@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _PLATFORM_SST_AUDIO_H_
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#define _PLATFORM_SST_AUDIO_H_
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#include <linux/sfi.h>
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#define MAX_NUM_STREAMS_MRFLD 25
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#define MAX_NUM_STREAMS MAX_NUM_STREAMS_MRFLD
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enum sst_audio_task_id_mrfld {
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SST_TASK_ID_NONE = 0,
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SST_TASK_ID_SBA = 1,
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SST_TASK_ID_MEDIA = 3,
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SST_TASK_ID_MAX = SST_TASK_ID_MEDIA,
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};
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/* Device IDs for Merrifield are Pipe IDs,
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* ref: DSP spec v0.75 */
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enum sst_audio_device_id_mrfld {
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/* Output pipeline IDs */
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PIPE_ID_OUT_START = 0x0,
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PIPE_CODEC_OUT0 = 0x2,
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PIPE_CODEC_OUT1 = 0x3,
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PIPE_SPROT_LOOP_OUT = 0x4,
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PIPE_MEDIA_LOOP1_OUT = 0x5,
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PIPE_MEDIA_LOOP2_OUT = 0x6,
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PIPE_VOIP_OUT = 0xC,
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PIPE_PCM0_OUT = 0xD,
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PIPE_PCM1_OUT = 0xE,
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PIPE_PCM2_OUT = 0xF,
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PIPE_MEDIA0_OUT = 0x12,
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PIPE_MEDIA1_OUT = 0x13,
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/* Input Pipeline IDs */
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PIPE_ID_IN_START = 0x80,
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PIPE_CODEC_IN0 = 0x82,
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PIPE_CODEC_IN1 = 0x83,
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PIPE_SPROT_LOOP_IN = 0x84,
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PIPE_MEDIA_LOOP1_IN = 0x85,
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PIPE_MEDIA_LOOP2_IN = 0x86,
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PIPE_VOIP_IN = 0x8C,
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PIPE_PCM0_IN = 0x8D,
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PIPE_PCM1_IN = 0x8E,
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PIPE_MEDIA0_IN = 0x8F,
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PIPE_MEDIA1_IN = 0x90,
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PIPE_MEDIA2_IN = 0x91,
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PIPE_RSVD = 0xFF,
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};
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/* The stream map for each platform consists of an array of the below
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* stream map structure.
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*/
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struct sst_dev_stream_map {
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u8 dev_num; /* device id */
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u8 subdev_num; /* substream */
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u8 direction;
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u8 device_id; /* fw id */
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u8 task_id; /* fw task */
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u8 status;
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};
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struct sst_platform_data {
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/* Intel software platform id*/
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struct sst_dev_stream_map *pdev_strm_map;
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unsigned int strm_map_size;
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};
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struct sst_info {
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u32 iram_start;
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u32 iram_end;
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bool iram_use;
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u32 dram_start;
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u32 dram_end;
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bool dram_use;
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u32 imr_start;
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u32 imr_end;
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bool imr_use;
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u32 mailbox_start;
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bool use_elf;
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bool lpe_viewpt_rqd;
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unsigned int max_streams;
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u32 dma_max_len;
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u8 num_probes;
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};
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struct sst_lib_dnld_info {
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unsigned int mod_base;
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unsigned int mod_end;
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unsigned int mod_table_offset;
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unsigned int mod_table_size;
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bool mod_ddr_dnld;
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};
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struct sst_platform_info {
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const struct sst_info *probe_data;
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const struct sst_ipc_info *ipc_info;
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const struct sst_lib_dnld_info *lib_info;
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};
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int add_sst_platform_device(void);
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#endif
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