Zhenyu Wang 16a02cf08a agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04 09:39:50 +00:00
..
2010-09-21 11:39:52 +01:00
2010-09-21 11:36:11 +01:00
2009-10-14 17:36:54 +02:00
2008-08-12 10:13:38 +10:00