Mischa Jonker 174ae4e96e ARCv2: IDU-intc: Add support for edge-triggered interrupts ... This adds support for an optional extra interrupt cell to specify edge vs level triggered. It is backward compatible with dts files with only one cell, and will default to level-triggered in such a case. Note that I had to make a change to idu_irq_set_affinity as well, as this function was setting the interrupt type to "level" unconditionally, since this was the only type supported previously. Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2019-08-26 22:34:59 +05:30
..
arc	ARCv2: IDU-intc: Add support for edge-triggered interrupts	2019-08-26 22:34:59 +05:30
at91	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
bcm2835	soc: bcm2835: sync firmware properties with downstream	2019-01-09 16:34:46 +01:00
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	NXP/FSL SoC driver updates for v5.3	2019-06-17 04:38:06 -07:00
imx	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mediatek	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
mscc	net: mscc: ocelot: simplify register access for PLL5 configuration	2018-10-05 14:36:44 -07:00
nps	soc: Support for NPS HW scheduling	2016-11-30 11:54:25 -08:00
qcom	soc: qcom: cmd-db: Stop memcpy()ing in cmd_db_read_aux_data()	2018-11-14 10:06:24 -08:00
rockchip	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
tegra	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00