linux/drivers/cxl
Dan Williams 176baefb2e cxl/hdm: Commit decoder state to hardware
After all the soft validation of the region has completed, convey the
region configuration to hardware while being careful to commit decoders
in specification mandated order. In addition to programming the endpoint
decoder base-address, interleave ways and granularity, the switch
decoder target lists are also established.

While the kernel can enforce spec-mandated commit order, it can not
enforce spec-mandated reset order. For example, the kernel can't stop
someone from removing an endpoint device that is occupying decoderN in a
switch decoder where decoderN+1 is also committed. To reset decoderN,
decoderN+1 must be torn down first. That "tear down the world"
implementation is saved for a follow-on patch.

Callback operations are provided for the 'commit' and 'reset'
operations. While those callbacks may prove useful for CXL accelerators
(Type-2 devices with memory) the primary motivation is to enable a
simple way for cxl_test to intercept those operations.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784338418.1758207.14659830845389904356.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-07-25 12:18:07 -07:00
..
core cxl/hdm: Commit decoder state to hardware 2022-07-25 12:18:07 -07:00
acpi.c cxl/port: Record parent dport when adding ports 2022-07-21 17:19:24 -07:00
cxl.h cxl/hdm: Commit decoder state to hardware 2022-07-25 12:18:07 -07:00
cxlmem.h cxl/region: Attach endpoint decoders 2022-07-25 12:18:07 -07:00
cxlpci.h cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00
Kconfig cxl/region: Allocate HPA capacity to regions 2022-07-25 12:18:06 -07:00
Makefile PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
mem.c cxl/mem: Enumerate port targets before adding endpoints 2022-07-21 17:19:25 -07:00
pci.c cxl/pci: Create PCI DOE mailbox's for memory devices 2022-07-19 15:38:04 -07:00
pmem.c cxl/mbox: Use __le32 in get,set_lsa mailbox structures 2022-06-21 14:09:00 -07:00
port.c cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00