Victor Lu 1972642843 drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2) ...

W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.

v2: rebase

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2023-11-09 17:03:16 -05:00

..

drm

drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2)

2023-11-09 17:03:16 -05:00

host1x

gpu: host1x: Correct allocated size for contexts

2023-10-11 22:52:44 +02:00

ipu-v3

drm for 6.6-rc1

2023-08-30 13:34:34 -07:00

trace

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vga

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Makefile

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