Peter De Schrijver 1a7da87727 clk: tegra: fix SS control on PLL enable/disable
PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-23 15:56:53 -07:00
..
2017-02-03 12:36:36 -08:00
2016-04-28 10:52:28 +02:00
2017-03-20 14:06:23 +01:00
2017-03-20 14:06:23 +01:00
2017-03-20 14:06:23 +01:00
2017-02-03 12:36:36 -08:00
2017-02-03 12:36:36 -08:00