Dan Williams 1b58b4cac6 cxl/port: Record parent dport when adding ports ... At the time that cxl_port instances are being created, cache the dport from the parent port that points to this new child port. This will be useful for region provisioning when walking the tree to calculate decoder targets, and saves rewalking the dport list after the fact to build this information. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-1-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-07-21 17:19:24 -07:00
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core	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
acpi.c	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
cxl.h	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
cxlmem.h	cxl/hdm: Enumerate allocated DPA	2022-07-21 17:19:12 -07:00
cxlpci.h	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
Kconfig	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
pci.c	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
pmem.c	cxl/mbox: Use __le32 in get,set_lsa mailbox structures	2022-06-21 14:09:00 -07:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00