1299a129a9
Move local_flush_tlb_all() earlier (just after setup_ptwalker() and before page allocation). This can avoid stale TLB entries misguiding the later page allocation. Without this patch the second kernel of kexec/kdump fails to boot SMP. BTW, move output_pgtable_bits_defines() into tlb_init() since it has nothing to do with tlb handler setup. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
308 lines
7.5 KiB
C
308 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/export.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/tlb.h>
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void local_flush_tlb_all(void)
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{
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invtlb_all(INVTLB_CURRENT_ALL, 0, 0);
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}
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EXPORT_SYMBOL(local_flush_tlb_all);
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void local_flush_tlb_user(void)
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{
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invtlb_all(INVTLB_CURRENT_GFALSE, 0, 0);
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}
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EXPORT_SYMBOL(local_flush_tlb_user);
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void local_flush_tlb_kernel(void)
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{
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invtlb_all(INVTLB_CURRENT_GTRUE, 0, 0);
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}
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EXPORT_SYMBOL(local_flush_tlb_kernel);
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/*
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* All entries common to a mm share an asid. To effectively flush
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* these entries, we just bump the asid.
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*/
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu;
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preempt_disable();
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cpu = smp_processor_id();
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if (asid_valid(mm, cpu))
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drop_mmu_context(mm, cpu);
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else
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cpumask_clear_cpu(cpu, mm_cpumask(mm));
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preempt_enable();
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int cpu = smp_processor_id();
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if (asid_valid(mm, cpu)) {
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unsigned long size, flags;
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local_irq_save(flags);
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start = round_down(start, PAGE_SIZE << 1);
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end = round_up(end, PAGE_SIZE << 1);
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size = (end - start) >> (PAGE_SHIFT + 1);
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if (size <= (current_cpu_data.tlbsizestlbsets ?
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current_cpu_data.tlbsize / 8 :
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current_cpu_data.tlbsize / 2)) {
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int asid = cpu_asid(cpu, mm);
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while (start < end) {
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invtlb(INVTLB_ADDR_GFALSE_AND_ASID, asid, start);
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start += (PAGE_SIZE << 1);
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}
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} else {
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drop_mmu_context(mm, cpu);
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}
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local_irq_restore(flags);
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} else {
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cpumask_clear_cpu(cpu, mm_cpumask(mm));
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}
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long size, flags;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= (current_cpu_data.tlbsizestlbsets ?
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current_cpu_data.tlbsize / 8 :
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current_cpu_data.tlbsize / 2)) {
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, start);
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start += (PAGE_SIZE << 1);
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}
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} else {
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local_flush_tlb_kernel();
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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int cpu = smp_processor_id();
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if (asid_valid(vma->vm_mm, cpu)) {
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int newpid;
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newpid = cpu_asid(cpu, vma->vm_mm);
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page &= (PAGE_MASK << 1);
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invtlb(INVTLB_ADDR_GFALSE_AND_ASID, newpid, page);
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} else {
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cpumask_clear_cpu(cpu, mm_cpumask(vma->vm_mm));
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}
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}
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/*
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* This one is only used for pages with the global bit set so we don't care
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* much about the ASID.
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*/
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void local_flush_tlb_one(unsigned long page)
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{
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page &= (PAGE_MASK << 1);
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invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, page);
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}
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static void __update_hugetlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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int idx;
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unsigned long lo;
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unsigned long flags;
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local_irq_save(flags);
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address &= (PAGE_MASK << 1);
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write_csr_entryhi(address);
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tlb_probe();
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idx = read_csr_tlbidx();
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write_csr_pagesize(PS_HUGE_SIZE);
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lo = pmd_to_entrylo(pte_val(*ptep));
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write_csr_entrylo0(lo);
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write_csr_entrylo1(lo + (HPAGE_SIZE >> 1));
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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write_csr_pagesize(PS_DEFAULT_SIZE);
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local_irq_restore(flags);
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#endif
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}
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
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int idx;
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unsigned long flags;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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if (pte_val(*ptep) & _PAGE_HUGE) {
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__update_hugetlb(vma, address, ptep);
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return;
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}
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local_irq_save(flags);
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if ((unsigned long)ptep & sizeof(pte_t))
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ptep--;
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address &= (PAGE_MASK << 1);
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write_csr_entryhi(address);
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tlb_probe();
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idx = read_csr_tlbidx();
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write_csr_pagesize(PS_DEFAULT_SIZE);
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write_csr_entrylo0(pte_val(*ptep++));
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write_csr_entrylo1(pte_val(*ptep));
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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local_irq_restore(flags);
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}
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static void setup_ptwalker(void)
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{
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unsigned long pwctl0, pwctl1;
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unsigned long pgd_i = 0, pgd_w = 0;
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unsigned long pud_i = 0, pud_w = 0;
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unsigned long pmd_i = 0, pmd_w = 0;
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unsigned long pte_i = 0, pte_w = 0;
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pgd_i = PGDIR_SHIFT;
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pgd_w = PAGE_SHIFT - 3;
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#if CONFIG_PGTABLE_LEVELS > 3
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pud_i = PUD_SHIFT;
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pud_w = PAGE_SHIFT - 3;
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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pmd_i = PMD_SHIFT;
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pmd_w = PAGE_SHIFT - 3;
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#endif
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pte_i = PAGE_SHIFT;
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pte_w = PAGE_SHIFT - 3;
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pwctl0 = pte_i | pte_w << 5 | pmd_i << 10 | pmd_w << 15 | pud_i << 20 | pud_w << 25;
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pwctl1 = pgd_i | pgd_w << 6;
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csr_write64(pwctl0, LOONGARCH_CSR_PWCTL0);
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csr_write64(pwctl1, LOONGARCH_CSR_PWCTL1);
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csr_write64((long)swapper_pg_dir, LOONGARCH_CSR_PGDH);
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csr_write64((long)invalid_pg_dir, LOONGARCH_CSR_PGDL);
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csr_write64((long)smp_processor_id(), LOONGARCH_CSR_TMID);
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}
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static void output_pgtable_bits_defines(void)
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{
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#define pr_define(fmt, ...) \
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pr_debug("#define " fmt, ##__VA_ARGS__)
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pr_debug("#include <asm/asm.h>\n");
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pr_debug("#include <asm/regdef.h>\n");
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pr_debug("\n");
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pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
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pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
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pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
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pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
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pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
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pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
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pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
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pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
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pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
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pr_debug("\n");
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}
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#ifdef CONFIG_NUMA
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static unsigned long pcpu_handlers[NR_CPUS];
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#endif
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extern long exception_handlers[VECSIZE * 128 / sizeof(long)];
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void setup_tlb_handler(int cpu)
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{
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setup_ptwalker();
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local_flush_tlb_all();
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/* The tlb handlers are generated only once */
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if (cpu == 0) {
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memcpy((void *)tlbrentry, handle_tlb_refill, 0x80);
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local_flush_icache_range(tlbrentry, tlbrentry + 0x80);
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set_handler(EXCCODE_TLBI * VECSIZE, handle_tlb_load, VECSIZE);
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set_handler(EXCCODE_TLBL * VECSIZE, handle_tlb_load, VECSIZE);
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set_handler(EXCCODE_TLBS * VECSIZE, handle_tlb_store, VECSIZE);
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set_handler(EXCCODE_TLBM * VECSIZE, handle_tlb_modify, VECSIZE);
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set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE);
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set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE);
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set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE);
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}
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#ifdef CONFIG_NUMA
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else {
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void *addr;
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struct page *page;
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const int vec_sz = sizeof(exception_handlers);
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if (pcpu_handlers[cpu])
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return;
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page = alloc_pages_node(cpu_to_node(cpu), GFP_ATOMIC, get_order(vec_sz));
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if (!page)
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return;
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addr = page_address(page);
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pcpu_handlers[cpu] = (unsigned long)addr;
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memcpy((void *)addr, (void *)eentry, vec_sz);
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local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_sz);
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csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY);
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csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY);
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csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY);
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}
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#endif
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}
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void tlb_init(int cpu)
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{
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write_csr_pagesize(PS_DEFAULT_SIZE);
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write_csr_stlbpgsize(PS_DEFAULT_SIZE);
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write_csr_tlbrefill_pagesize(PS_DEFAULT_SIZE);
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setup_tlb_handler(cpu);
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output_pgtable_bits_defines();
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}
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