4132a778e8
Add a new function to configure the shared clock between two i2s ports, and export it. This will allow the clock sharing to be set from the machine driver instead of the devicetree. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220908161154.648557-9-nfraprado@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
199 lines
4.5 KiB
C
199 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* mt8186-afe-common.h -- Mediatek 8186 audio driver definitions
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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*/
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#ifndef _MT_8186_AFE_COMMON_H_
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#define _MT_8186_AFE_COMMON_H_
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#include <sound/soc.h>
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include "mt8186-reg.h"
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#include "../common/mtk-base-afe.h"
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enum {
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MT8186_MEMIF_DL1,
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MT8186_MEMIF_DL12,
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MT8186_MEMIF_DL2,
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MT8186_MEMIF_DL3,
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MT8186_MEMIF_DL4,
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MT8186_MEMIF_DL5,
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MT8186_MEMIF_DL6,
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MT8186_MEMIF_DL7,
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MT8186_MEMIF_DL8,
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MT8186_MEMIF_VUL12,
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MT8186_MEMIF_VUL2,
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MT8186_MEMIF_VUL3,
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MT8186_MEMIF_VUL4,
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MT8186_MEMIF_VUL5,
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MT8186_MEMIF_VUL6,
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MT8186_MEMIF_AWB,
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MT8186_MEMIF_AWB2,
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MT8186_MEMIF_NUM,
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MT8186_DAI_ADDA = MT8186_MEMIF_NUM,
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MT8186_DAI_AP_DMIC,
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MT8186_DAI_CONNSYS_I2S,
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MT8186_DAI_I2S_0,
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MT8186_DAI_I2S_1,
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MT8186_DAI_I2S_2,
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MT8186_DAI_I2S_3,
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MT8186_DAI_HW_GAIN_1,
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MT8186_DAI_HW_GAIN_2,
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MT8186_DAI_SRC_1,
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MT8186_DAI_SRC_2,
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MT8186_DAI_PCM,
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MT8186_DAI_TDM_IN,
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MT8186_DAI_HOSTLESS_LPBK,
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MT8186_DAI_HOSTLESS_FM,
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MT8186_DAI_HOSTLESS_HW_GAIN_AAUDIO,
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MT8186_DAI_HOSTLESS_SRC_AAUDIO,
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MT8186_DAI_HOSTLESS_SRC_1,
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MT8186_DAI_HOSTLESS_SRC_BARGEIN,
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MT8186_DAI_HOSTLESS_UL1,
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MT8186_DAI_HOSTLESS_UL2,
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MT8186_DAI_HOSTLESS_UL3,
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MT8186_DAI_HOSTLESS_UL5,
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MT8186_DAI_HOSTLESS_UL6,
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MT8186_DAI_NUM,
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};
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#define MT8186_RECORD_MEMIF MT8186_MEMIF_VUL12
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#define MT8186_ECHO_REF_MEMIF MT8186_MEMIF_AWB
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#define MT8186_PRIMARY_MEMIF MT8186_MEMIF_DL1
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#define MT8186_FAST_MEMIF MT8186_MEMIF_DL2
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#define MT8186_DEEP_MEMIF MT8186_MEMIF_DL3
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#define MT8186_VOIP_MEMIF MT8186_MEMIF_DL12
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#define MT8186_MMAP_DL_MEMIF MT8186_MEMIF_DL5
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#define MT8186_MMAP_UL_MEMIF MT8186_MEMIF_VUL5
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#define MT8186_BARGEIN_MEMIF MT8186_MEMIF_AWB
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enum {
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MT8186_IRQ_0,
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MT8186_IRQ_1,
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MT8186_IRQ_2,
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MT8186_IRQ_3,
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MT8186_IRQ_4,
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MT8186_IRQ_5,
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MT8186_IRQ_6,
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MT8186_IRQ_7,
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MT8186_IRQ_8,
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MT8186_IRQ_9,
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MT8186_IRQ_10,
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MT8186_IRQ_11,
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MT8186_IRQ_12,
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MT8186_IRQ_13,
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MT8186_IRQ_14,
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MT8186_IRQ_15,
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MT8186_IRQ_16,
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MT8186_IRQ_17,
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MT8186_IRQ_18,
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MT8186_IRQ_19,
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MT8186_IRQ_20,
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MT8186_IRQ_21,
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MT8186_IRQ_22,
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MT8186_IRQ_23,
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MT8186_IRQ_24,
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MT8186_IRQ_25,
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MT8186_IRQ_26,
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MT8186_IRQ_NUM,
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};
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enum {
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MT8186_AFE_IRQ_DIR_MCU = 0,
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MT8186_AFE_IRQ_DIR_DSP,
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MT8186_AFE_IRQ_DIR_BOTH,
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};
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enum {
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MTKAIF_PROTOCOL_1 = 0,
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MTKAIF_PROTOCOL_2,
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MTKAIF_PROTOCOL_2_CLK_P2,
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};
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enum {
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MTK_AFE_ADDA_DL_GAIN_MUTE = 0,
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MTK_AFE_ADDA_DL_GAIN_NORMAL = 0xf74f,
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/* SA suggest apply -0.3db to audio/speech path */
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};
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#define MTK_SPK_I2S_0_STR "MTK_SPK_I2S_0"
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#define MTK_SPK_I2S_1_STR "MTK_SPK_I2S_1"
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#define MTK_SPK_I2S_2_STR "MTK_SPK_I2S_2"
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#define MTK_SPK_I2S_3_STR "MTK_SPK_I2S_3"
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/* MCLK */
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enum {
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MT8186_I2S0_MCK = 0,
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MT8186_I2S1_MCK,
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MT8186_I2S2_MCK,
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MT8186_I2S4_MCK,
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MT8186_TDM_MCK,
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MT8186_MCK_NUM,
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};
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struct snd_pcm_substream;
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struct mtk_base_irq_data;
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struct clk;
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struct mt8186_afe_private {
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struct clk **clk;
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struct clk_lookup **lookup;
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struct regmap *topckgen;
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struct regmap *apmixedsys;
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struct regmap *infracfg;
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int irq_cnt[MT8186_MEMIF_NUM];
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int stf_positive_gain_db;
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int pm_runtime_bypass_reg_ctl;
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int sgen_mode;
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int sgen_rate;
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int sgen_amplitude;
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/* xrun assert */
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int xrun_assert[MT8186_MEMIF_NUM];
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/* dai */
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bool dai_on[MT8186_DAI_NUM];
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void *dai_priv[MT8186_DAI_NUM];
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/* adda */
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bool mtkaif_calibration_ok;
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int mtkaif_protocol;
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int mtkaif_chosen_phase[4];
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int mtkaif_phase_cycle[4];
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int mtkaif_calibration_num_phase;
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int mtkaif_dmic;
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int mtkaif_looback0;
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int mtkaif_looback1;
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/* mck */
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int mck_rate[MT8186_MCK_NUM];
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};
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int mt8186_dai_adda_register(struct mtk_base_afe *afe);
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int mt8186_dai_i2s_register(struct mtk_base_afe *afe);
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int mt8186_dai_tdm_register(struct mtk_base_afe *afe);
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int mt8186_dai_hw_gain_register(struct mtk_base_afe *afe);
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int mt8186_dai_src_register(struct mtk_base_afe *afe);
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int mt8186_dai_pcm_register(struct mtk_base_afe *afe);
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int mt8186_dai_hostless_register(struct mtk_base_afe *afe);
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int mt8186_add_misc_control(struct snd_soc_component *component);
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unsigned int mt8186_general_rate_transform(struct device *dev,
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unsigned int rate);
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unsigned int mt8186_rate_transform(struct device *dev,
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unsigned int rate, int aud_blk);
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unsigned int mt8186_tdm_relatch_rate_transform(struct device *dev,
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unsigned int rate);
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int mt8186_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
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const char *secondary_i2s_name);
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int mt8186_dai_set_priv(struct mtk_base_afe *afe, int id,
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int priv_size, const void *priv_data);
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#endif
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