53dd7b1fb4
Several of the register updates that are currently done in the clock gating init functions are actually display workarounds that should move into the display-specific part of the code. Furthermore, some of the registers being programmed don't even have anything to do with clock gating at all. Extract the display workarounds for gen11 and later platforms to a dedicated display/intel_display_wa.c file to keep these separate from the SOC / sgunit clock gating that we need on some platforms. The gen11 cutoff here is selected somewhat arbitrarily; this is the point where workarounds were first assigned dedicated lineage numbers that can be easily looked up and confirmed in the modern workaround database. It also avoids any confusion on older platforms where the exact boundaries between display/GT/other IP blocks wasn't as well-defined as it is today. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907001009.3732474-2-matthew.d.roper@intel.com
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_wa.h"
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static void gen11_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_1409120013 */
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intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/* Wa_14010594013 */
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intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
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}
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static void xe_d_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_1409120013 */
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intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/* Wa_14013723622 */
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intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
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}
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static void adlp_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_22011091694:adlp */
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intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
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/* Bspec/49189 Initialize Sequence */
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intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
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}
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void intel_display_wa_apply(struct drm_i915_private *i915)
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{
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if (IS_ALDERLAKE_P(i915))
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adlp_display_wa_apply(i915);
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else if (DISPLAY_VER(i915) == 12)
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xe_d_display_wa_apply(i915);
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else if (DISPLAY_VER(i915) == 11)
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gen11_display_wa_apply(i915);
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}
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