dd2a93a814
Vendor capabilities occupy 0x8000 to 0xFFFF according to CXL 2.0 spec 8.2.8.2.1 CXL Device Capabilities. While they are not defined by the spec, they are allowed and not "unknown". Call this detail out in the logs to let users easily distinguish the difference. This patch is a squash of two earlier patches and take in some minor suggestions from both Vishal and Dan. Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/20210520204852.1070780-1-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include "cxl.h"
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/**
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* DOC: cxl core
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*
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* The CXL core provides a sysfs hierarchy for control devices and a rendezvous
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* point for cross-device interleave coordination through cxl ports.
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*/
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/**
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* cxl_setup_device_regs() - Detect CXL Device register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
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* @regs: Base pointers for device register blocks (see CXL_DEVICE_REGS())
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*/
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void cxl_setup_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_regs *regs)
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{
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int cap, cap_count;
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u64 cap_array;
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*regs = (struct cxl_device_regs) { 0 };
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cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return;
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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u32 offset;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(base + cap * 0x10));
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offset = readl(base + cap * 0x10 + 0x4);
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register_block = base + offset;
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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regs->status = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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regs->mbox = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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regs->memdev = register_block;
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break;
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default:
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if (cap_id >= 0x8000)
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dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset);
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else
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dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_setup_device_regs);
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struct bus_type cxl_bus_type = {
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.name = "cxl",
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};
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EXPORT_SYMBOL_GPL(cxl_bus_type);
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static __init int cxl_core_init(void)
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{
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return bus_register(&cxl_bus_type);
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}
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static void cxl_core_exit(void)
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{
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bus_unregister(&cxl_bus_type);
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}
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module_init(cxl_core_init);
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module_exit(cxl_core_exit);
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MODULE_LICENSE("GPL v2");
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