1d7ecc8084
DSU-110 is the newest and shiniest for Armv9. Its programmer's model is largely identical to the previous generation of DSUs, so we can treat it as compatible, but it does have a a handful of extra IMP-DEF PMU events to call its own. Thanks to the new notion of core complexes, the maximum number of supported CPUs goes up as well. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/51a8060493e1220886dcd468fad9a2b603607297.1639490264.git.robin.murphy@arm.com Signed-off-by: Rob Herring <robh@kernel.org>
46 lines
1.3 KiB
YAML
46 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2021 Arm Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
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maintainers:
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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- Robin Murphy <robin.murphy@arm.com>
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description:
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ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
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L3 memory system, control logic and external interfaces to form a multicore
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cluster. The PMU enables gathering various statistics on the operation of the
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DSU. The PMU provides independent 32-bit counters that can count any of the
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supported events, along with a 64-bit cycle counter. The PMU is accessed via
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CPU system registers and has no MMIO component.
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properties:
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compatible:
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oneOf:
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- const: arm,dsu-pmu
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- items:
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- const: arm,dsu-110-pmu
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- const: arm,dsu-pmu
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interrupts:
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items:
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- description: nCLUSTERPMUIRQ interrupt
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cpus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 12
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description: List of phandles for the CPUs connected to this DSU instance.
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required:
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- compatible
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- interrupts
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- cpus
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additionalProperties: false
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