17bd3a1e10
The true check on the variable startable in the ternary operator
is always false because the previous if statement handles the true
condition for startable. Hence the ternary check is dead code and
can be removed.
Addresses-Coverity: ("Logically dead code")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
548 lines
16 KiB
C
548 lines
16 KiB
C
/*
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drivers/net/ethernet/dec/tulip/media.c
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Copyright 2000,2001 The Linux Kernel Team
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Written/copyright 1994-2001 by Donald Becker.
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This software may be used and distributed according to the terms
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of the GNU General Public License, incorporated herein by reference.
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Please submit bugs to http://bugzilla.kernel.org/ .
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*/
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include "tulip.h"
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/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
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met by back-to-back PCI I/O cycles, but we insert a delay to avoid
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"overclocking" issues or future 66Mhz PCI. */
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#define mdio_delay() ioread32(mdio_addr)
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/* Read and write the MII registers using software-generated serial
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MDIO protocol. It is just different enough from the EEPROM protocol
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to not share code. The maxium data clock rate is 2.5 Mhz. */
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#define MDIO_SHIFT_CLK 0x10000
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#define MDIO_DATA_WRITE0 0x00000
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#define MDIO_DATA_WRITE1 0x20000
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#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
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#define MDIO_ENB_IN 0x40000
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#define MDIO_DATA_READ 0x80000
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static const unsigned char comet_miireg2offset[32] = {
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0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
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0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
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/* MII transceiver control section.
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Read and write the MII registers using software-generated serial
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MDIO protocol.
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See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
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or DP83840A data sheet for more details.
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*/
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int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
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{
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struct tulip_private *tp = netdev_priv(dev);
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int i;
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int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
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int retval = 0;
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void __iomem *ioaddr = tp->base_addr;
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void __iomem *mdio_addr = ioaddr + CSR9;
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unsigned long flags;
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if (location & ~0x1f)
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return 0xffff;
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if (tp->chip_id == COMET && phy_id == 30) {
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if (comet_miireg2offset[location])
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return ioread32(ioaddr + comet_miireg2offset[location]);
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return 0xffff;
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}
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spin_lock_irqsave(&tp->mii_lock, flags);
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if (tp->chip_id == LC82C168) {
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iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
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ioread32(ioaddr + 0xA0);
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ioread32(ioaddr + 0xA0);
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for (i = 1000; i >= 0; --i) {
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barrier();
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if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
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break;
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}
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spin_unlock_irqrestore(&tp->mii_lock, flags);
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return retval & 0xffff;
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}
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/* Establish sync by sending at least 32 logic ones. */
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for (i = 32; i >= 0; i--) {
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iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
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mdio_delay();
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iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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/* Shift the read command bits out. */
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for (i = 15; i >= 0; i--) {
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int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
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iowrite32(MDIO_ENB | dataval, mdio_addr);
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mdio_delay();
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iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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/* Read the two transition, 16 data, and wire-idle bits. */
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for (i = 19; i > 0; i--) {
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iowrite32(MDIO_ENB_IN, mdio_addr);
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mdio_delay();
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retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
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iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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spin_unlock_irqrestore(&tp->mii_lock, flags);
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return (retval>>1) & 0xffff;
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}
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void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
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{
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struct tulip_private *tp = netdev_priv(dev);
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int i;
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int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
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void __iomem *ioaddr = tp->base_addr;
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void __iomem *mdio_addr = ioaddr + CSR9;
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unsigned long flags;
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if (location & ~0x1f)
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return;
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if (tp->chip_id == COMET && phy_id == 30) {
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if (comet_miireg2offset[location])
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iowrite32(val, ioaddr + comet_miireg2offset[location]);
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return;
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}
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spin_lock_irqsave(&tp->mii_lock, flags);
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if (tp->chip_id == LC82C168) {
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iowrite32(cmd, ioaddr + 0xA0);
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for (i = 1000; i >= 0; --i) {
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barrier();
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if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
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break;
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}
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spin_unlock_irqrestore(&tp->mii_lock, flags);
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return;
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}
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/* Establish sync by sending 32 logic ones. */
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for (i = 32; i >= 0; i--) {
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iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
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mdio_delay();
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iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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/* Shift the command bits out. */
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for (i = 31; i >= 0; i--) {
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int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
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iowrite32(MDIO_ENB | dataval, mdio_addr);
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mdio_delay();
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iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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/* Clear out extra bits. */
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for (i = 2; i > 0; i--) {
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iowrite32(MDIO_ENB_IN, mdio_addr);
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mdio_delay();
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iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
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mdio_delay();
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}
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spin_unlock_irqrestore(&tp->mii_lock, flags);
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}
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/* Set up the transceiver control registers for the selected media type. */
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void tulip_select_media(struct net_device *dev, int startup)
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{
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struct tulip_private *tp = netdev_priv(dev);
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void __iomem *ioaddr = tp->base_addr;
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struct mediatable *mtable = tp->mtable;
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u32 new_csr6;
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int i;
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if (mtable) {
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struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
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unsigned char *p = mleaf->leafdata;
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switch (mleaf->type) {
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case 0: /* 21140 non-MII xcvr. */
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if (tulip_debug > 1)
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netdev_dbg(dev, "Using a 21140 non-MII transceiver with control setting %02x\n",
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p[1]);
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dev->if_port = p[0];
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if (startup)
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iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
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iowrite32(p[1], ioaddr + CSR12);
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new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
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break;
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case 2: case 4: {
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u16 setup[5];
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u32 csr13val, csr14val, csr15dir, csr15val;
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for (i = 0; i < 5; i++)
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setup[i] = get_u16(&p[i*2 + 1]);
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dev->if_port = p[0] & MEDIA_MASK;
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if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
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tp->full_duplex = 1;
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if (startup && mtable->has_reset) {
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struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
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unsigned char *rst = rleaf->leafdata;
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if (tulip_debug > 1)
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netdev_dbg(dev, "Resetting the transceiver\n");
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for (i = 0; i < rst[0]; i++)
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iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
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}
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if (tulip_debug > 1)
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netdev_dbg(dev, "21143 non-MII %s transceiver control %04x/%04x\n",
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medianame[dev->if_port],
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setup[0], setup[1]);
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if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
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csr13val = setup[0];
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csr14val = setup[1];
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csr15dir = (setup[3]<<16) | setup[2];
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csr15val = (setup[4]<<16) | setup[2];
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iowrite32(0, ioaddr + CSR13);
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iowrite32(csr14val, ioaddr + CSR14);
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iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
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iowrite32(csr15val, ioaddr + CSR15); /* Data */
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iowrite32(csr13val, ioaddr + CSR13);
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} else {
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csr13val = 1;
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csr14val = 0;
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csr15dir = (setup[0]<<16) | 0x0008;
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csr15val = (setup[1]<<16) | 0x0008;
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if (dev->if_port <= 4)
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csr14val = t21142_csr14[dev->if_port];
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if (startup) {
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iowrite32(0, ioaddr + CSR13);
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iowrite32(csr14val, ioaddr + CSR14);
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}
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iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
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iowrite32(csr15val, ioaddr + CSR15); /* Data */
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if (startup) iowrite32(csr13val, ioaddr + CSR13);
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}
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if (tulip_debug > 1)
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netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
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csr15dir, csr15val);
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if (mleaf->type == 4)
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new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
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else
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new_csr6 = 0x82420000;
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break;
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}
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case 1: case 3: {
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int phy_num = p[0];
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int init_length = p[1];
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u16 *misc_info, tmp_info;
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dev->if_port = 11;
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new_csr6 = 0x020E0000;
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if (mleaf->type == 3) { /* 21142 */
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u16 *init_sequence = (u16*)(p+2);
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u16 *reset_sequence = &((u16*)(p+3))[init_length];
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int reset_length = p[2 + init_length*2];
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misc_info = reset_sequence + reset_length;
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if (startup) {
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int timeout = 10; /* max 1 ms */
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for (i = 0; i < reset_length; i++)
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iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
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/* flush posted writes */
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ioread32(ioaddr + CSR15);
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/* Sect 3.10.3 in DP83840A.pdf (p39) */
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udelay(500);
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/* Section 4.2 in DP83840A.pdf (p43) */
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/* and IEEE 802.3 "22.2.4.1.1 Reset" */
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while (timeout-- &&
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(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
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udelay(100);
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}
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for (i = 0; i < init_length; i++)
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iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
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ioread32(ioaddr + CSR15); /* flush posted writes */
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} else {
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u8 *init_sequence = p + 2;
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u8 *reset_sequence = p + 3 + init_length;
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int reset_length = p[2 + init_length];
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misc_info = (u16*)(reset_sequence + reset_length);
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if (startup) {
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int timeout = 10; /* max 1 ms */
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iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
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for (i = 0; i < reset_length; i++)
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iowrite32(reset_sequence[i], ioaddr + CSR12);
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/* flush posted writes */
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ioread32(ioaddr + CSR12);
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/* Sect 3.10.3 in DP83840A.pdf (p39) */
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udelay(500);
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/* Section 4.2 in DP83840A.pdf (p43) */
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/* and IEEE 802.3 "22.2.4.1.1 Reset" */
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while (timeout-- &&
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(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
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udelay(100);
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}
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for (i = 0; i < init_length; i++)
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iowrite32(init_sequence[i], ioaddr + CSR12);
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ioread32(ioaddr + CSR12); /* flush posted writes */
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}
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tmp_info = get_u16(&misc_info[1]);
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if (tmp_info)
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tp->advertising[phy_num] = tmp_info | 1;
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if (tmp_info && startup < 2) {
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if (tp->mii_advertise == 0)
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tp->mii_advertise = tp->advertising[phy_num];
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if (tulip_debug > 1)
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netdev_dbg(dev, " Advertising %04x on MII %d\n",
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tp->mii_advertise,
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tp->phys[phy_num]);
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tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
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}
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break;
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}
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case 5: case 6: {
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new_csr6 = 0; /* FIXME */
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if (startup && mtable->has_reset) {
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struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
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unsigned char *rst = rleaf->leafdata;
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if (tulip_debug > 1)
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netdev_dbg(dev, "Resetting the transceiver\n");
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for (i = 0; i < rst[0]; i++)
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iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
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}
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break;
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}
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default:
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netdev_dbg(dev, " Invalid media table selection %d\n",
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mleaf->type);
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new_csr6 = 0x020E0000;
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}
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if (tulip_debug > 1)
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netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
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medianame[dev->if_port],
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ioread32(ioaddr + CSR12) & 0xff);
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} else if (tp->chip_id == LC82C168) {
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if (startup && ! tp->medialock)
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dev->if_port = tp->mii_cnt ? 11 : 0;
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if (tulip_debug > 1)
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netdev_dbg(dev, "PNIC PHY status is %3.3x, media %s\n",
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ioread32(ioaddr + 0xB8),
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medianame[dev->if_port]);
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if (tp->mii_cnt) {
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new_csr6 = 0x810C0000;
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iowrite32(0x0001, ioaddr + CSR15);
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iowrite32(0x0201B07A, ioaddr + 0xB8);
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} else if (startup) {
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/* Start with 10mbps to do autonegotiation. */
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iowrite32(0x32, ioaddr + CSR12);
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new_csr6 = 0x00420000;
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iowrite32(0x0001B078, ioaddr + 0xB8);
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iowrite32(0x0201B078, ioaddr + 0xB8);
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} else if (dev->if_port == 3 || dev->if_port == 5) {
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iowrite32(0x33, ioaddr + CSR12);
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new_csr6 = 0x01860000;
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/* Trigger autonegotiation. */
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iowrite32(0x0001F868, ioaddr + 0xB8);
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} else {
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iowrite32(0x32, ioaddr + CSR12);
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new_csr6 = 0x00420000;
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iowrite32(0x1F078, ioaddr + 0xB8);
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}
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} else { /* Unknown chip type with no media table. */
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if (tp->default_port == 0)
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dev->if_port = tp->mii_cnt ? 11 : 3;
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if (tulip_media_cap[dev->if_port] & MediaIsMII) {
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new_csr6 = 0x020E0000;
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} else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
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new_csr6 = 0x02860000;
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} else
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new_csr6 = 0x03860000;
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if (tulip_debug > 1)
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netdev_dbg(dev, "No media description table, assuming %s transceiver, CSR12 %02x\n",
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medianame[dev->if_port],
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ioread32(ioaddr + CSR12));
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}
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tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
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mdelay(1);
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}
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/*
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Check the MII negotiated duplex and change the CSR6 setting if
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required.
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Return 0 if everything is OK.
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Return < 0 if the transceiver is missing or has no link beat.
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*/
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int tulip_check_duplex(struct net_device *dev)
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{
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struct tulip_private *tp = netdev_priv(dev);
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unsigned int bmsr, lpa, negotiated, new_csr6;
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bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
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lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
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if (tulip_debug > 1)
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dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n",
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bmsr, lpa);
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if (bmsr == 0xffff)
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return -2;
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if ((bmsr & BMSR_LSTATUS) == 0) {
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int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
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if ((new_bmsr & BMSR_LSTATUS) == 0) {
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if (tulip_debug > 1)
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dev_info(&dev->dev,
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"No link beat on the MII interface, status %04x\n",
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new_bmsr);
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return -1;
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}
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}
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negotiated = lpa & tp->advertising[0];
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|
tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
|
|
|
|
new_csr6 = tp->csr6;
|
|
|
|
if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
|
|
else new_csr6 |= TxThreshold;
|
|
if (tp->full_duplex) new_csr6 |= FullDuplex;
|
|
else new_csr6 &= ~FullDuplex;
|
|
|
|
if (new_csr6 != tp->csr6) {
|
|
tp->csr6 = new_csr6;
|
|
tulip_restart_rxtx(tp);
|
|
|
|
if (tulip_debug > 0)
|
|
dev_info(&dev->dev,
|
|
"Setting %s-duplex based on MII#%d link partner capability of %04x\n",
|
|
tp->full_duplex ? "full" : "half",
|
|
tp->phys[0], lpa);
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void tulip_find_mii(struct net_device *dev, int board_idx)
|
|
{
|
|
struct tulip_private *tp = netdev_priv(dev);
|
|
int phyn, phy_idx = 0;
|
|
int mii_reg0;
|
|
int mii_advert;
|
|
unsigned int to_advert, new_bmcr, ane_switch;
|
|
|
|
/* Find the connected MII xcvrs.
|
|
Doing this in open() would allow detecting external xcvrs later,
|
|
but takes much time. */
|
|
for (phyn = 1; phyn <= 32 && phy_idx < ARRAY_SIZE(tp->phys); phyn++) {
|
|
int phy = phyn & 0x1f;
|
|
int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
|
|
if ((mii_status & 0x8301) == 0x8001 ||
|
|
((mii_status & BMSR_100BASE4) == 0 &&
|
|
(mii_status & 0x7800) != 0)) {
|
|
/* preserve Becker logic, gain indentation level */
|
|
} else {
|
|
continue;
|
|
}
|
|
|
|
mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
|
|
mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
|
|
ane_switch = 0;
|
|
|
|
/* if not advertising at all, gen an
|
|
* advertising value from the capability
|
|
* bits in BMSR
|
|
*/
|
|
if ((mii_advert & ADVERTISE_ALL) == 0) {
|
|
unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
|
|
mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
|
|
}
|
|
|
|
if (tp->mii_advertise) {
|
|
tp->advertising[phy_idx] =
|
|
to_advert = tp->mii_advertise;
|
|
} else if (tp->advertising[phy_idx]) {
|
|
to_advert = tp->advertising[phy_idx];
|
|
} else {
|
|
tp->advertising[phy_idx] =
|
|
tp->mii_advertise =
|
|
to_advert = mii_advert;
|
|
}
|
|
|
|
tp->phys[phy_idx++] = phy;
|
|
|
|
pr_info("tulip%d: MII transceiver #%d config %04x status %04x advertising %04x\n",
|
|
board_idx, phy, mii_reg0, mii_status, mii_advert);
|
|
|
|
/* Fixup for DLink with miswired PHY. */
|
|
if (mii_advert != to_advert) {
|
|
pr_debug("tulip%d: Advertising %04x on PHY %d, previously advertising %04x\n",
|
|
board_idx, to_advert, phy, mii_advert);
|
|
tulip_mdio_write (dev, phy, 4, to_advert);
|
|
}
|
|
|
|
/* Enable autonegotiation: some boards default to off. */
|
|
if (tp->default_port == 0) {
|
|
new_bmcr = mii_reg0 | BMCR_ANENABLE;
|
|
if (new_bmcr != mii_reg0) {
|
|
new_bmcr |= BMCR_ANRESTART;
|
|
ane_switch = 1;
|
|
}
|
|
}
|
|
/* ...or disable nway, if forcing media */
|
|
else {
|
|
new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
|
|
if (new_bmcr != mii_reg0)
|
|
ane_switch = 1;
|
|
}
|
|
|
|
/* clear out bits we never want at this point */
|
|
new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
|
|
BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
|
|
BMCR_RESET);
|
|
|
|
if (tp->full_duplex)
|
|
new_bmcr |= BMCR_FULLDPLX;
|
|
if (tulip_media_cap[tp->default_port] & MediaIs100)
|
|
new_bmcr |= BMCR_SPEED100;
|
|
|
|
if (new_bmcr != mii_reg0) {
|
|
/* some phys need the ANE switch to
|
|
* happen before forced media settings
|
|
* will "take." However, we write the
|
|
* same value twice in order not to
|
|
* confuse the sane phys.
|
|
*/
|
|
if (ane_switch) {
|
|
tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
|
|
udelay (10);
|
|
}
|
|
tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
|
|
}
|
|
}
|
|
tp->mii_cnt = phy_idx;
|
|
if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
|
|
pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",
|
|
board_idx);
|
|
tp->phys[0] = 1;
|
|
}
|
|
}
|