1e859d3e03
The alpha value calculation has been written for 40-bit alpha values which doesn't work work properly for 16-bit ones. The alpha value is calculated on the basis of ALPHA_BITWIDTH to make the computation easy for 40 bit alpha. After calculating the 32 bit alpha, it is converted to 40 bit alpha by making lower bits zero. But if actual alpha register width is less than ALPHA_BITWIDTH, then the actual width can be used for calculation. This also means, during the 40 bit alpha pll set rate path, the lower alpha register is not configured Change the code to calculate the rate and register values from 'alpha_width' instead of hard-coding it so that it can work for the different widths that are supported. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
108 lines
2.4 KiB
C
108 lines
2.4 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_ALPHA_PLL_H__
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#define __QCOM_CLK_ALPHA_PLL_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/* Alpha PLL types */
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enum {
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CLK_ALPHA_PLL_TYPE_DEFAULT,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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enum {
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PLL_OFF_L_VAL,
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PLL_OFF_ALPHA_VAL,
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PLL_OFF_ALPHA_VAL_U,
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PLL_OFF_USER_CTL,
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PLL_OFF_USER_CTL_U,
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PLL_OFF_CONFIG_CTL,
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PLL_OFF_CONFIG_CTL_U,
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PLL_OFF_TEST_CTL,
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PLL_OFF_TEST_CTL_U,
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PLL_OFF_STATUS,
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PLL_OFF_MAX_REGS
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};
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extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
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struct pll_vco {
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unsigned long min_freq;
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unsigned long max_freq;
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u32 val;
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};
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/**
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* struct clk_alpha_pll - phase locked loop (PLL)
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* @offset: base address of registers
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* @vco_table: array of VCO settings
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* @regs: alpha pll register map (see @clk_alpha_pll_regs)
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll {
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u32 offset;
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const u8 *regs;
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const struct pll_vco *vco_table;
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size_t num_vco;
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#define SUPPORTS_OFFLINE_REQ BIT(0)
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#define SUPPORTS_FSM_MODE BIT(2)
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u8 flags;
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struct clk_regmap clkr;
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};
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/**
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* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
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* @offset: base address of registers
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* @regs: alpha pll register map (see @clk_alpha_pll_regs)
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* @width: width of post-divider
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll_postdiv {
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u32 offset;
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u8 width;
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const u8 *regs;
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struct clk_regmap clkr;
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};
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struct alpha_pll_config {
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u32 l;
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u32 alpha;
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u32 config_ctl_val;
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u32 config_ctl_hi_val;
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u32 main_output_mask;
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u32 aux_output_mask;
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u32 aux2_output_mask;
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u32 early_output_mask;
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u32 pre_div_val;
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u32 pre_div_mask;
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u32 post_div_val;
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u32 post_div_mask;
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u32 vco_val;
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u32 vco_mask;
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};
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extern const struct clk_ops clk_alpha_pll_ops;
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extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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#endif
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