65371a3f14
Add a sub-driver for SDIO based chipsets which implements the following functionality: - register accessors for 8, 16 and 32 bits for all states of the card (including usage of 4x 8 bit access for one 32 bit buffer if the card is not fully powered on yet - or if it's fully powered on then 1x 32 bit access is used) - checking whether there's space in the TX FIFO queue to transmit data - transfers from the host to the device for actual network traffic, reserved pages (for firmware download) and H2C (host-to-card) transfers - receiving data from the device - deep power saving state The transmit path is optimized so DMA-capable SDIO host controllers can directly use the buffers provided because the buffer's physical addresses are 8 byte aligned. The receive path is prepared to support RX aggregation where the chipset combines multiple MAC frames into one bigger buffer to reduce SDIO transfer overhead. Co-developed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230405200729.632435-3-martin.blumenstingl@googlemail.com
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_MAC_H__
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#define __RTW_MAC_H__
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#define RTW_HW_PORT_NUM 5
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#define cut_version_to_mask(cut) (0x1 << ((cut) + 1))
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#define DDMA_POLLING_COUNT 1000
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#define C2H_PKT_BUF 256
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#define REPORT_BUF 128
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#define PHY_STATUS_SIZE 4
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#define ILLEGAL_KEY_GROUP 0xFAAAAA00
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/* HW memory address */
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#define OCPBASE_RXBUF_FW_88XX 0x18680000
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#define OCPBASE_TXBUF_88XX 0x18780000
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#define OCPBASE_ROM_88XX 0x00000000
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#define OCPBASE_IMEM_88XX 0x00030000
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#define OCPBASE_DMEM_88XX 0x00200000
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#define OCPBASE_EMEM_88XX 0x00100000
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#define RSVD_PG_DRV_NUM 16
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#define RSVD_PG_H2C_EXTRAINFO_NUM 24
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#define RSVD_PG_H2C_STATICINFO_NUM 8
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#define RSVD_PG_H2CQ_NUM 8
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#define RSVD_PG_CPU_INSTRUCTION_NUM 0
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#define RSVD_PG_FW_TXBUF_NUM 4
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void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_ch_idx);
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int rtw_mac_power_on(struct rtw_dev *rtwdev);
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void rtw_mac_power_off(struct rtw_dev *rtwdev);
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int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw);
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int rtw_mac_init(struct rtw_dev *rtwdev);
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void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop);
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int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size);
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static inline void rtw_mac_flush_all_queues(struct rtw_dev *rtwdev, bool drop)
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{
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rtw_mac_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, drop);
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}
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#endif
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