5098e2b95e
I have hit the following build error:
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o: in function `pinconf_generic_dt_node_to_map_pin':
pmc.c:(.text+0x500): undefined reference to `pinconf_generic_dt_node_to_map'
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o:(.rodata+0x1f88): undefined reference to `pinconf_generic_dt_free_map'
So SOC_TEGRA_PMC should select GENERIC_PINCONF.
Fixes: 4a37f11c8f ("soc/tegra: pmc: Implement pad configuration via pinctrl")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
150 lines
4.1 KiB
Plaintext
150 lines
4.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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if ARCH_TEGRA
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# 32-bit ARM SoCs
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if ARM
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config ARCH_TEGRA_2x_SOC
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bool "Enable support for Tegra20 family"
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select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
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select ARM_ERRATA_720789
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select ARM_ERRATA_754327 if SMP
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA20
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select SOC_TEGRA20_VOLTAGE_COUPLER
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config ARCH_TEGRA_3x_SOC
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bool "Enable support for Tegra30 family"
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA30
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select SOC_TEGRA30_VOLTAGE_COUPLER
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config ARCH_TEGRA_114_SOC
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bool "Enable support for Tegra114 family"
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA114
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T114 processor family, based on the
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ARM CortexA15MP CPU
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config ARCH_TEGRA_124_SOC
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bool "Enable support for Tegra124 family"
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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ARM CortexA15MP CPU
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endif
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# 64-bit ARM SoCs
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if ARM64
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config ARCH_TEGRA_132_SOC
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bool "NVIDIA Tegra132 SoC"
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select PINCTRL_TEGRA124
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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help
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Enable support for NVIDIA Tegra132 SoC, based on the Denver
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ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
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but contains an NVIDIA Denver CPU complex in place of
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Tegra124's "4+1" Cortex-A15 CPU complex.
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config ARCH_TEGRA_210_SOC
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bool "NVIDIA Tegra210 SoC"
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select PINCTRL_TEGRA210
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
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the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
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cores in a switched configuration. It features a GPU of the Maxwell
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architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
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and providing 256 CUDA cores. It supports hardware-accelerated en-
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and decoding of various video standards including H.265, H.264 and
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VP8 at 4K resolution and up to 60 fps.
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Besides the multimedia features it also comes with a variety of I/O
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controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
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name only a few.
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config ARCH_TEGRA_186_SOC
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bool "NVIDIA Tegra186 SoC"
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select MAILBOX
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select TEGRA_BPMP
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select TEGRA_HSP_MBOX
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select TEGRA_IVC
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select SOC_TEGRA_PMC
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help
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Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
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combination of Denver and Cortex-A57 CPU cores and a GPU based on
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the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
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used for audio processing, hardware video encoders/decoders with
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multi-format support, ISP for image capture processing and BPMP for
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power management.
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config ARCH_TEGRA_194_SOC
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bool "NVIDIA Tegra194 SoC"
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select MAILBOX
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select PINCTRL_TEGRA194
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select TEGRA_BPMP
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select TEGRA_HSP_MBOX
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select TEGRA_IVC
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select SOC_TEGRA_PMC
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help
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Enable support for the NVIDIA Tegra194 SoC.
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endif
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endif
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config SOC_TEGRA_FUSE
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def_bool y
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depends on ARCH_TEGRA
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select SOC_BUS
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select TEGRA20_APB_DMA if ARCH_TEGRA_2x_SOC
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config SOC_TEGRA_FLOWCTRL
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bool
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config SOC_TEGRA_PMC
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bool
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select GENERIC_PINCONF
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config SOC_TEGRA_POWERGATE_BPMP
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def_bool y
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depends on PM_GENERIC_DOMAINS
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depends on TEGRA_BPMP
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config SOC_TEGRA20_VOLTAGE_COUPLER
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bool "Voltage scaling support for Tegra20 SoCs"
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depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
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config SOC_TEGRA30_VOLTAGE_COUPLER
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bool "Voltage scaling support for Tegra30 SoCs"
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depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
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