c9b258c6be
Add initial hook up code to implement generic IO page table framework. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Link: https://lore.kernel.org/r/20201215073705.123786-3-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CPU-agnostic AMD IO page table allocator.
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*
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* Copyright (C) 2020 Advanced Micro Devices, Inc.
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* Author: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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*/
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#define pr_fmt(fmt) "AMD-Vi: " fmt
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#define dev_fmt(fmt) pr_fmt(fmt)
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#include <linux/atomic.h>
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#include <linux/bitops.h>
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#include <linux/io-pgtable.h>
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <asm/barrier.h>
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#include "amd_iommu_types.h"
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#include "amd_iommu.h"
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static void v1_tlb_flush_all(void *cookie)
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{
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}
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static void v1_tlb_flush_walk(unsigned long iova, size_t size,
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size_t granule, void *cookie)
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{
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}
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static void v1_tlb_add_page(struct iommu_iotlb_gather *gather,
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unsigned long iova, size_t granule,
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void *cookie)
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{
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}
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static const struct iommu_flush_ops v1_flush_ops = {
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.tlb_flush_all = v1_tlb_flush_all,
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.tlb_flush_walk = v1_tlb_flush_walk,
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.tlb_add_page = v1_tlb_add_page,
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};
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/*
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* ----------------------------------------------------
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*/
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static void v1_free_pgtable(struct io_pgtable *iop)
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{
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}
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static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
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{
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struct amd_io_pgtable *pgtable = io_pgtable_cfg_to_data(cfg);
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cfg->pgsize_bitmap = AMD_IOMMU_PGSIZES,
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cfg->ias = IOMMU_IN_ADDR_BIT_SIZE,
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cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE,
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cfg->tlb = &v1_flush_ops;
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return &pgtable->iop;
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}
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struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns = {
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.alloc = v1_alloc_pgtable,
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.free = v1_free_pgtable,
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};
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