Xing Zheng 20c389e656 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12 10:04:52 +02:00
..
2016-04-15 16:02:16 -07:00
2015-11-10 15:00:03 -08:00
2016-04-15 16:50:01 -07:00
2016-03-02 17:44:59 -08:00
2016-04-15 16:50:04 -07:00
2016-03-02 17:46:55 -08:00
2016-08-01 18:37:45 -04:00
2016-07-12 11:24:07 +02:00
2016-04-15 16:50:07 -07:00
2016-03-02 17:48:26 -08:00
2015-07-20 11:11:32 -07:00
2016-03-02 17:48:47 -08:00
2016-04-15 16:50:10 -07:00
2016-03-03 11:27:48 -08:00
2015-07-20 11:11:33 -07:00
2016-04-15 16:50:12 -07:00
2016-04-15 16:50:14 -07:00
2016-04-19 18:56:15 -07:00
2016-04-15 16:50:18 -07:00
2016-03-02 17:50:58 -08:00
2016-07-06 17:55:31 -07:00
2016-04-15 16:50:21 -07:00
2016-04-15 16:50:23 -07:00
2016-04-15 16:50:27 -07:00
2016-07-12 15:31:21 -07:00
2016-07-19 09:53:52 -07:00