bd4ba605c4
According to PCIe spec, Enable Relaxed Ordering value in the VF's PCI config space is wired to 0 and PF relaxed ordering (RO) setting should be applied to the VF. In QEMU (and maybe others), when assigning VFs, the RO bit in PCI config space is not emulated properly and is always set to 0. Therefore, pcie_relaxed_ordering_enabled() always returns 0 for VFs and VMs and thus MKeys can't be created with RO read even if the PF supports it. pcie_relaxed_ordering_enabled() check was added to avoid a syndrome when creating a MKey with relaxed ordering (RO) enabled when the driver's relaxed_ordering_read_pci_enabled HCA capability is out of sync with FW. With the new relaxed_ordering_read capability this can't happen, as it's set regardless of RO value in PCI config space and thus can't change during runtime. Hence, to allow RO read in VFs and VMs, use the new HCA capability relaxed_ordering_read without checking pcie_relaxed_ordering_enabled(). The old capability checks are kept for backward compatibility with older FWs. Allowing RO in VFs and VMs is valuable since it can greatly improve performance on some setups. For example, testing throughput of a VF on an AMD EPYC 7763 and ConnectX-6 Dx setup showed roughly 60% performance improvement. Signed-off-by: Avihai Horon <avihaih@nvidia.com> Reviewed-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Aya Levin <ayal@nvidia.com> Link: https://lore.kernel.org/r/e7048640d66c341a8fa0465e099926e7989184bc.1681131553.git.leon@kernel.org Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
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#ifndef _MLX5_IB_UMR_H
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#define _MLX5_IB_UMR_H
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#include "mlx5_ib.h"
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#define MLX5_MAX_UMR_SHIFT 16
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#define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
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#define MLX5_IB_UMR_OCTOWORD 16
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#define MLX5_IB_UMR_XLT_ALIGNMENT 64
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int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev);
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void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev);
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static inline bool mlx5r_umr_can_load_pas(struct mlx5_ib_dev *dev,
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size_t length)
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{
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/*
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* umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is
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* always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka
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* MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey
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* can never be enabled without this capability. Simplify this weird
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* quirky hardware by just saying it can't use PAS lists with UMR at
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* all.
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*/
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if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
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return false;
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/*
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* length is the size of the MR in bytes when mlx5_ib_update_xlt() is
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* used.
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*/
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if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
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length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE)
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return false;
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return true;
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}
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/*
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* true if an existing MR can be reconfigured to new access_flags using UMR.
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* Older HW cannot use UMR to update certain elements of the MKC. See
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* get_umr_update_access_mask() and umr_check_mkey_mask()
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*/
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static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev,
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unsigned int current_access_flags,
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unsigned int target_access_flags)
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{
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unsigned int diffs = current_access_flags ^ target_access_flags;
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if ((diffs & IB_ACCESS_REMOTE_ATOMIC) &&
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MLX5_CAP_GEN(dev->mdev, atomic) &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
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return false;
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if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
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return false;
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if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
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(MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
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return false;
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return true;
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}
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static inline u64 mlx5r_umr_get_xlt_octo(u64 bytes)
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{
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return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
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MLX5_IB_UMR_OCTOWORD;
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}
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struct mlx5r_umr_context {
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struct ib_cqe cqe;
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enum ib_wc_status status;
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struct completion done;
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};
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struct mlx5r_umr_wqe {
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struct mlx5_wqe_umr_ctrl_seg ctrl_seg;
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struct mlx5_mkey_seg mkey_seg;
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struct mlx5_wqe_data_seg data_seg;
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};
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int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr);
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int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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int access_flags);
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int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
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int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags);
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#endif /* _MLX5_IB_UMR_H */
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