21b43bd59c
There's a bunch of strange things about this code. First up is that none of the fields being written to are functional for a VF. The SR-IOV specification lists then as "Reserved, but OS should preserve" so writing new values to them doesn't do anything and is clearly wrong from a correctness perspective. However, since VFs are designed to be managed by the OS there is an argument to be made that we should be saving and restoring some parts of config space. We already sort of do that by saving the first 64 bytes of config space in the eeh_dev (see eeh_dev->config_space[]). This is inadequate since it doesn't even consider saving and restoring the PCI capability structures. However, this is a problem with EEH in general and that needs to be fixed for non-VF devices too. There's no real reason to keep around this around so delete it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200725081231.39076-6-oohall@gmail.com
959 lines
25 KiB
C
959 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* The file intends to implement the platform dependent EEH operations on pseries.
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* Actually, the pseries platform is built based on RTAS heavily. That means the
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* pseries platform dependent EEH operations will be built on RTAS calls. The functions
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* are derived from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
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* been done.
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*
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* Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
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* Copyright IBM Corporation 2001, 2005, 2006
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* Copyright Dave Engebretsen & Todd Inglett 2001
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* Copyright Linas Vepstas 2005, 2006
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*/
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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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#include <linux/rbtree.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <linux/crash_dump.h>
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#include <asm/eeh.h>
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#include <asm/eeh_event.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/rtas.h>
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static int pseries_eeh_get_pe_addr(struct pci_dn *pdn);
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/* RTAS tokens */
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static int ibm_set_eeh_option;
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static int ibm_set_slot_reset;
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static int ibm_read_slot_reset_state;
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static int ibm_read_slot_reset_state2;
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static int ibm_slot_error_detail;
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static int ibm_get_config_addr_info;
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static int ibm_get_config_addr_info2;
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static int ibm_configure_pe;
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void pseries_pcibios_bus_add_device(struct pci_dev *pdev)
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{
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struct pci_dn *pdn = pci_get_pdn(pdev);
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if (eeh_has_flag(EEH_FORCE_DISABLED))
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return;
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dev_dbg(&pdev->dev, "EEH: Setting up device\n");
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#ifdef CONFIG_PCI_IOV
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if (pdev->is_virtfn) {
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pdn->device_id = pdev->device;
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pdn->vendor_id = pdev->vendor;
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pdn->class_code = pdev->class;
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/*
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* Last allow unfreeze return code used for retrieval
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* by user space in eeh-sysfs to show the last command
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* completion from platform.
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*/
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pdn->last_allow_rc = 0;
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}
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#endif
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pseries_eeh_init_edev(pdn);
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#ifdef CONFIG_PCI_IOV
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if (pdev->is_virtfn) {
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struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
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edev->pe_config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
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eeh_rmv_from_parent_pe(edev); /* Remove as it is adding to bus pe */
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eeh_add_to_parent_pe(edev); /* Add as VF PE type */
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}
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#endif
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eeh_probe_device(pdev);
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}
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/**
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* pseries_eeh_get_config_addr - Retrieve config address
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*
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* Retrieve the assocated config address. Actually, there're 2 RTAS
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* function calls dedicated for the purpose. We need implement
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* it through the new function and then the old one. Besides,
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* you should make sure the config address is figured out from
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* FDT node before calling the function.
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*
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* It's notable that zero'ed return value means invalid PE config
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* address.
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*/
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static int pseries_eeh_get_config_addr(struct pci_controller *phb, int config_addr)
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{
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int ret = 0;
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int rets[3];
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if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
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/*
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* First of all, we need to make sure there has one PE
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* associated with the device. Otherwise, PE address is
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* meaningless.
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*/
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ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid), 1);
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if (ret || (rets[0] == 0))
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return 0;
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/* Retrieve the associated PE config address */
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ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid), 0);
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if (ret) {
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pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
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__func__, phb->global_number, config_addr);
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return 0;
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}
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return rets[0];
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}
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if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
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ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid), 0);
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if (ret) {
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pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
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__func__, phb->global_number, config_addr);
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return 0;
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}
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return rets[0];
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}
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return ret;
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}
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/**
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* pseries_eeh_phb_reset - Reset the specified PHB
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* @phb: PCI controller
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* @config_adddr: the associated config address
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* @option: reset option
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*
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* Reset the specified PHB/PE
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*/
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static int pseries_eeh_phb_reset(struct pci_controller *phb, int config_addr, int option)
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{
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int ret;
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/* Reset PE through RTAS call */
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ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid), option);
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/* If fundamental-reset not supported, try hot-reset */
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if (option == EEH_RESET_FUNDAMENTAL &&
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ret == -8) {
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option = EEH_RESET_HOT;
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ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid), option);
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}
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/* We need reset hold or settlement delay */
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if (option == EEH_RESET_FUNDAMENTAL ||
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option == EEH_RESET_HOT)
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msleep(EEH_PE_RST_HOLD_TIME);
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else
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msleep(EEH_PE_RST_SETTLE_TIME);
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return ret;
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}
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/**
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* pseries_eeh_phb_configure_bridge - Configure PCI bridges in the indicated PE
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* @phb: PCI controller
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* @config_adddr: the associated config address
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*
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* The function will be called to reconfigure the bridges included
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* in the specified PE so that the mulfunctional PE would be recovered
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* again.
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*/
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static int pseries_eeh_phb_configure_bridge(struct pci_controller *phb, int config_addr)
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{
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int ret;
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/* Waiting 0.2s maximum before skipping configuration */
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int max_wait = 200;
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while (max_wait > 0) {
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ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
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config_addr, BUID_HI(phb->buid),
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BUID_LO(phb->buid));
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if (!ret)
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return ret;
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if (ret < 0)
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break;
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/*
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* If RTAS returns a delay value that's above 100ms, cut it
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* down to 100ms in case firmware made a mistake. For more
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* on how these delay values work see rtas_busy_delay_time
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*/
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if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
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ret <= RTAS_EXTENDED_DELAY_MAX)
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ret = RTAS_EXTENDED_DELAY_MIN+2;
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max_wait -= rtas_busy_delay_time(ret);
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if (max_wait < 0)
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break;
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rtas_busy_delay(ret);
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}
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pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
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__func__, phb->global_number, config_addr, ret);
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/* PAPR defines -3 as "Parameter Error" for this function: */
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if (ret == -3)
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return -EINVAL;
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else
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return -EIO;
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}
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/*
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* Buffer for reporting slot-error-detail rtas calls. Its here
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* in BSS, and not dynamically alloced, so that it ends up in
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* RMO where RTAS can access it.
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*/
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static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
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static DEFINE_SPINLOCK(slot_errbuf_lock);
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static int eeh_error_buf_size;
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/**
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* pseries_eeh_init - EEH platform dependent initialization
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*
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* EEH platform dependent initialization on pseries.
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*/
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static int pseries_eeh_init(void)
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{
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struct pci_controller *phb;
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struct pci_dn *pdn;
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int addr, config_addr;
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/* figure out EEH RTAS function call tokens */
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ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
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ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
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ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
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ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
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ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
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ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
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ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
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ibm_configure_pe = rtas_token("ibm,configure-pe");
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/*
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* ibm,configure-pe and ibm,configure-bridge have the same semantics,
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* however ibm,configure-pe can be faster. If we can't find
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* ibm,configure-pe then fall back to using ibm,configure-bridge.
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*/
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if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
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ibm_configure_pe = rtas_token("ibm,configure-bridge");
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/*
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* Necessary sanity check. We needn't check "get-config-addr-info"
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* and its variant since the old firmware probably support address
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* of domain/bus/slot/function for EEH RTAS operations.
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*/
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if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE ||
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ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE ||
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(ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
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ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
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ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE ||
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ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
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pr_info("EEH functionality not supported\n");
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return -EINVAL;
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}
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/* Initialize error log lock and size */
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spin_lock_init(&slot_errbuf_lock);
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eeh_error_buf_size = rtas_token("rtas-error-log-max");
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if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
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pr_info("%s: unknown EEH error log size\n",
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__func__);
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eeh_error_buf_size = 1024;
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} else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
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pr_info("%s: EEH error log size %d exceeds the maximal %d\n",
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__func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
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eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
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}
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/* Set EEH probe mode */
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eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
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/* Set EEH machine dependent code */
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ppc_md.pcibios_bus_add_device = pseries_pcibios_bus_add_device;
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if (is_kdump_kernel() || reset_devices) {
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pr_info("Issue PHB reset ...\n");
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list_for_each_entry(phb, &hose_list, list_node) {
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pdn = list_first_entry(&PCI_DN(phb->dn)->child_list, struct pci_dn, list);
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addr = (pdn->busno << 16) | (pdn->devfn << 8);
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config_addr = pseries_eeh_get_config_addr(phb, addr);
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/* invalid PE config addr */
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if (config_addr == 0)
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continue;
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pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_FUNDAMENTAL);
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pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_DEACTIVATE);
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pseries_eeh_phb_configure_bridge(phb, config_addr);
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}
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}
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return 0;
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}
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static int pseries_eeh_cap_start(struct pci_dn *pdn)
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{
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u32 status;
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if (!pdn)
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return 0;
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rtas_read_config(pdn, PCI_STATUS, 2, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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return PCI_CAPABILITY_LIST;
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}
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static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
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{
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int pos = pseries_eeh_cap_start(pdn);
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int cnt = 48; /* Maximal number of capabilities */
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u32 id;
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if (!pos)
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return 0;
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while (cnt--) {
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rtas_read_config(pdn, pos, 1, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
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{
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struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
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u32 header;
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int pos = 256;
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int ttl = (4096 - 256) / 8;
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if (!edev || !edev->pcie_cap)
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return 0;
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if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
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return 0;
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else if (!header)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap && pos)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < 256)
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break;
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if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
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break;
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}
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return 0;
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}
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/**
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* pseries_eeh_init_edev - initialise the eeh_dev and eeh_pe for a pci_dn
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*
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* @pdn: PCI device node
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*
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* When we discover a new PCI device via the device-tree we create a
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* corresponding pci_dn and we allocate, but don't initialise, an eeh_dev.
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* This function takes care of the initialisation and inserts the eeh_dev
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* into the correct eeh_pe. If no eeh_pe exists we'll allocate one.
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*/
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void pseries_eeh_init_edev(struct pci_dn *pdn)
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{
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struct eeh_dev *edev;
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struct eeh_pe pe;
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u32 pcie_flags;
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int enable = 0;
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int ret;
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if (WARN_ON_ONCE(!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)))
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return;
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/*
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* Find the eeh_dev for this pdn. The storage for the eeh_dev was
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* allocated at the same time as the pci_dn.
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*
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* XXX: We should probably re-visit that.
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*/
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edev = pdn_to_eeh_dev(pdn);
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if (!edev)
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return;
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/*
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* If ->pe is set then we've already probed this device. We hit
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* this path when a pci_dev is removed and rescanned while recovering
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* a PE (i.e. for devices where the driver doesn't support error
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* recovery).
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*/
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if (edev->pe)
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return;
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/* Check class/vendor/device IDs */
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if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
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return;
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/* Skip for PCI-ISA bridge */
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if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
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return;
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eeh_edev_dbg(edev, "Probing device\n");
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/*
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* Update class code and mode of eeh device. We need
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* correctly reflects that current device is root port
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* or PCIe switch downstream port.
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*/
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edev->class_code = pdn->class_code;
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edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
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edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
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edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
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edev->mode &= 0xFFFFFF00;
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if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
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edev->mode |= EEH_DEV_BRIDGE;
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if (edev->pcie_cap) {
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rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
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2, &pcie_flags);
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pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
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if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
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edev->mode |= EEH_DEV_ROOT_PORT;
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else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
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edev->mode |= EEH_DEV_DS_PORT;
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}
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}
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|
|
/* Initialize the fake PE */
|
|
memset(&pe, 0, sizeof(struct eeh_pe));
|
|
pe.phb = pdn->phb;
|
|
pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
|
|
|
|
/* Enable EEH on the device */
|
|
eeh_edev_dbg(edev, "Enabling EEH on device\n");
|
|
ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
|
|
if (ret) {
|
|
eeh_edev_dbg(edev, "EEH failed to enable on device (code %d)\n", ret);
|
|
} else {
|
|
/* Retrieve PE address */
|
|
edev->pe_config_addr = pseries_eeh_get_pe_addr(pdn);
|
|
pe.addr = edev->pe_config_addr;
|
|
|
|
/* Some older systems (Power4) allow the ibm,set-eeh-option
|
|
* call to succeed even on nodes where EEH is not supported.
|
|
* Verify support explicitly.
|
|
*/
|
|
ret = eeh_ops->get_state(&pe, NULL);
|
|
if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
|
|
enable = 1;
|
|
|
|
if (enable) {
|
|
eeh_add_flag(EEH_ENABLED);
|
|
eeh_add_to_parent_pe(edev);
|
|
} else if (pdn->parent && pdn_to_eeh_dev(pdn->parent) &&
|
|
(pdn_to_eeh_dev(pdn->parent))->pe) {
|
|
/* This device doesn't support EEH, but it may have an
|
|
* EEH parent, in which case we mark it as supported.
|
|
*/
|
|
edev->pe_config_addr = pdn_to_eeh_dev(pdn->parent)->pe_config_addr;
|
|
eeh_add_to_parent_pe(edev);
|
|
}
|
|
eeh_edev_dbg(edev, "EEH is %s on device (code %d)\n",
|
|
(enable ? "enabled" : "unsupported"), ret);
|
|
}
|
|
|
|
/* Save memory bars */
|
|
eeh_save_bars(edev);
|
|
}
|
|
|
|
static struct eeh_dev *pseries_eeh_probe(struct pci_dev *pdev)
|
|
{
|
|
struct eeh_dev *edev;
|
|
struct pci_dn *pdn;
|
|
|
|
pdn = pci_get_pdn_by_devfn(pdev->bus, pdev->devfn);
|
|
if (!pdn)
|
|
return NULL;
|
|
|
|
/*
|
|
* If the system supports EEH on this device then the eeh_dev was
|
|
* configured and inserted into a PE in pseries_eeh_init_edev()
|
|
*/
|
|
edev = pdn_to_eeh_dev(pdn);
|
|
if (!edev || !edev->pe)
|
|
return NULL;
|
|
|
|
return edev;
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_init_edev_recursive - Enable EEH for the indicated device
|
|
* @pdn: PCI device node
|
|
*
|
|
* This routine must be used to perform EEH initialization for the
|
|
* indicated PCI device that was added after system boot (e.g.
|
|
* hotplug, dlpar).
|
|
*/
|
|
void pseries_eeh_init_edev_recursive(struct pci_dn *pdn)
|
|
{
|
|
struct pci_dn *n;
|
|
|
|
if (!pdn)
|
|
return;
|
|
|
|
list_for_each_entry(n, &pdn->child_list, list)
|
|
pseries_eeh_init_edev_recursive(n);
|
|
|
|
pseries_eeh_init_edev(pdn);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pseries_eeh_init_edev_recursive);
|
|
|
|
/**
|
|
* pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
|
|
* @pe: EEH PE
|
|
* @option: operation to be issued
|
|
*
|
|
* The function is used to control the EEH functionality globally.
|
|
* Currently, following options are support according to PAPR:
|
|
* Enable EEH, Disable EEH, Enable MMIO and Enable DMA
|
|
*/
|
|
static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
|
|
{
|
|
int ret = 0;
|
|
int config_addr;
|
|
|
|
/*
|
|
* When we're enabling or disabling EEH functioality on
|
|
* the particular PE, the PE config address is possibly
|
|
* unavailable. Therefore, we have to figure it out from
|
|
* the FDT node.
|
|
*/
|
|
switch (option) {
|
|
case EEH_OPT_DISABLE:
|
|
case EEH_OPT_ENABLE:
|
|
case EEH_OPT_THAW_MMIO:
|
|
case EEH_OPT_THAW_DMA:
|
|
config_addr = pe->config_addr;
|
|
if (pe->addr)
|
|
config_addr = pe->addr;
|
|
break;
|
|
case EEH_OPT_FREEZE_PE:
|
|
/* Not support */
|
|
return 0;
|
|
default:
|
|
pr_err("%s: Invalid option %d\n",
|
|
__func__, option);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
|
|
config_addr, BUID_HI(pe->phb->buid),
|
|
BUID_LO(pe->phb->buid), option);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_get_pe_addr - Retrieve PE address
|
|
* @pe: EEH PE
|
|
*
|
|
* Retrieve the assocated PE address. Actually, there're 2 RTAS
|
|
* function calls dedicated for the purpose. We need implement
|
|
* it through the new function and then the old one. Besides,
|
|
* you should make sure the config address is figured out from
|
|
* FDT node before calling the function.
|
|
*
|
|
* It's notable that zero'ed return value means invalid PE config
|
|
* address.
|
|
*/
|
|
static int pseries_eeh_get_pe_addr(struct pci_dn *pdn)
|
|
{
|
|
int config_addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
|
|
unsigned long buid = pdn->phb->buid;
|
|
int ret = 0;
|
|
int rets[3];
|
|
|
|
if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
|
|
/*
|
|
* First of all, we need to make sure there has one PE
|
|
* associated with the device. Otherwise, PE address is
|
|
* meaningless.
|
|
*/
|
|
ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
|
|
config_addr, BUID_HI(buid), BUID_LO(buid), 1);
|
|
if (ret || (rets[0] == 0))
|
|
return 0;
|
|
|
|
/* Retrieve the associated PE config address */
|
|
ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
|
|
config_addr, BUID_HI(buid), BUID_LO(buid), 0);
|
|
if (ret) {
|
|
pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
|
|
__func__, pdn->phb->global_number, config_addr);
|
|
return 0;
|
|
}
|
|
|
|
return rets[0];
|
|
}
|
|
|
|
if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
|
|
ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
|
|
config_addr, BUID_HI(buid), BUID_LO(buid), 0);
|
|
if (ret) {
|
|
pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
|
|
__func__, pdn->phb->global_number, config_addr);
|
|
return 0;
|
|
}
|
|
|
|
return rets[0];
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_get_state - Retrieve PE state
|
|
* @pe: EEH PE
|
|
* @delay: suggested time to wait if state is unavailable
|
|
*
|
|
* Retrieve the state of the specified PE. On RTAS compliant
|
|
* pseries platform, there already has one dedicated RTAS function
|
|
* for the purpose. It's notable that the associated PE config address
|
|
* might be ready when calling the function. Therefore, endeavour to
|
|
* use the PE config address if possible. Further more, there're 2
|
|
* RTAS calls for the purpose, we need to try the new one and back
|
|
* to the old one if the new one couldn't work properly.
|
|
*/
|
|
static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
|
|
{
|
|
int config_addr;
|
|
int ret;
|
|
int rets[4];
|
|
int result;
|
|
|
|
/* Figure out PE config address if possible */
|
|
config_addr = pe->config_addr;
|
|
if (pe->addr)
|
|
config_addr = pe->addr;
|
|
|
|
if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
|
|
ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
|
|
config_addr, BUID_HI(pe->phb->buid),
|
|
BUID_LO(pe->phb->buid));
|
|
} else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
|
|
/* Fake PE unavailable info */
|
|
rets[2] = 0;
|
|
ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
|
|
config_addr, BUID_HI(pe->phb->buid),
|
|
BUID_LO(pe->phb->buid));
|
|
} else {
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Parse the result out */
|
|
if (!rets[1])
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
|
|
switch(rets[0]) {
|
|
case 0:
|
|
result = EEH_STATE_MMIO_ACTIVE |
|
|
EEH_STATE_DMA_ACTIVE;
|
|
break;
|
|
case 1:
|
|
result = EEH_STATE_RESET_ACTIVE |
|
|
EEH_STATE_MMIO_ACTIVE |
|
|
EEH_STATE_DMA_ACTIVE;
|
|
break;
|
|
case 2:
|
|
result = 0;
|
|
break;
|
|
case 4:
|
|
result = EEH_STATE_MMIO_ENABLED;
|
|
break;
|
|
case 5:
|
|
if (rets[2]) {
|
|
if (delay)
|
|
*delay = rets[2];
|
|
result = EEH_STATE_UNAVAILABLE;
|
|
} else {
|
|
result = EEH_STATE_NOT_SUPPORT;
|
|
}
|
|
break;
|
|
default:
|
|
result = EEH_STATE_NOT_SUPPORT;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_reset - Reset the specified PE
|
|
* @pe: EEH PE
|
|
* @option: reset option
|
|
*
|
|
* Reset the specified PE
|
|
*/
|
|
static int pseries_eeh_reset(struct eeh_pe *pe, int option)
|
|
{
|
|
int config_addr;
|
|
|
|
/* Figure out PE address */
|
|
config_addr = pe->config_addr;
|
|
if (pe->addr)
|
|
config_addr = pe->addr;
|
|
|
|
return pseries_eeh_phb_reset(pe->phb, config_addr, option);
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_get_log - Retrieve error log
|
|
* @pe: EEH PE
|
|
* @severity: temporary or permanent error log
|
|
* @drv_log: driver log to be combined with retrieved error log
|
|
* @len: length of driver log
|
|
*
|
|
* Retrieve the temporary or permanent error from the PE.
|
|
* Actually, the error will be retrieved through the dedicated
|
|
* RTAS call.
|
|
*/
|
|
static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
|
|
{
|
|
int config_addr;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&slot_errbuf_lock, flags);
|
|
memset(slot_errbuf, 0, eeh_error_buf_size);
|
|
|
|
/* Figure out the PE address */
|
|
config_addr = pe->config_addr;
|
|
if (pe->addr)
|
|
config_addr = pe->addr;
|
|
|
|
ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
|
|
BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
|
|
virt_to_phys(drv_log), len,
|
|
virt_to_phys(slot_errbuf), eeh_error_buf_size,
|
|
severity);
|
|
if (!ret)
|
|
log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
|
|
spin_unlock_irqrestore(&slot_errbuf_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
|
|
* @pe: EEH PE
|
|
*
|
|
*/
|
|
static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
|
|
{
|
|
int config_addr;
|
|
|
|
/* Figure out the PE address */
|
|
config_addr = pe->config_addr;
|
|
if (pe->addr)
|
|
config_addr = pe->addr;
|
|
|
|
return pseries_eeh_phb_configure_bridge(pe->phb, config_addr);
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_read_config - Read PCI config space
|
|
* @pdn: PCI device node
|
|
* @where: PCI address
|
|
* @size: size to read
|
|
* @val: return value
|
|
*
|
|
* Read config space from the speicifed device
|
|
*/
|
|
static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
|
|
{
|
|
return rtas_read_config(pdn, where, size, val);
|
|
}
|
|
|
|
/**
|
|
* pseries_eeh_write_config - Write PCI config space
|
|
* @pdn: PCI device node
|
|
* @where: PCI address
|
|
* @size: size to write
|
|
* @val: value to be written
|
|
*
|
|
* Write config space to the specified device
|
|
*/
|
|
static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val)
|
|
{
|
|
return rtas_write_config(pdn, where, size, val);
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
int pseries_send_allow_unfreeze(struct pci_dn *pdn,
|
|
u16 *vf_pe_array, int cur_vfs)
|
|
{
|
|
int rc;
|
|
int ibm_allow_unfreeze = rtas_token("ibm,open-sriov-allow-unfreeze");
|
|
unsigned long buid, addr;
|
|
|
|
addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
|
|
buid = pdn->phb->buid;
|
|
spin_lock(&rtas_data_buf_lock);
|
|
memcpy(rtas_data_buf, vf_pe_array, RTAS_DATA_BUF_SIZE);
|
|
rc = rtas_call(ibm_allow_unfreeze, 5, 1, NULL,
|
|
addr,
|
|
BUID_HI(buid),
|
|
BUID_LO(buid),
|
|
rtas_data_buf, cur_vfs * sizeof(u16));
|
|
spin_unlock(&rtas_data_buf_lock);
|
|
if (rc)
|
|
pr_warn("%s: Failed to allow unfreeze for PHB#%x-PE#%lx, rc=%x\n",
|
|
__func__,
|
|
pdn->phb->global_number, addr, rc);
|
|
return rc;
|
|
}
|
|
|
|
static int pseries_call_allow_unfreeze(struct eeh_dev *edev)
|
|
{
|
|
int cur_vfs = 0, rc = 0, vf_index, bus, devfn, vf_pe_num;
|
|
struct pci_dn *pdn, *tmp, *parent, *physfn_pdn;
|
|
u16 *vf_pe_array;
|
|
|
|
vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
|
|
if (!vf_pe_array)
|
|
return -ENOMEM;
|
|
if (pci_num_vf(edev->physfn ? edev->physfn : edev->pdev)) {
|
|
if (edev->pdev->is_physfn) {
|
|
cur_vfs = pci_num_vf(edev->pdev);
|
|
pdn = eeh_dev_to_pdn(edev);
|
|
parent = pdn->parent;
|
|
for (vf_index = 0; vf_index < cur_vfs; vf_index++)
|
|
vf_pe_array[vf_index] =
|
|
cpu_to_be16(pdn->pe_num_map[vf_index]);
|
|
rc = pseries_send_allow_unfreeze(pdn, vf_pe_array,
|
|
cur_vfs);
|
|
pdn->last_allow_rc = rc;
|
|
for (vf_index = 0; vf_index < cur_vfs; vf_index++) {
|
|
list_for_each_entry_safe(pdn, tmp,
|
|
&parent->child_list,
|
|
list) {
|
|
bus = pci_iov_virtfn_bus(edev->pdev,
|
|
vf_index);
|
|
devfn = pci_iov_virtfn_devfn(edev->pdev,
|
|
vf_index);
|
|
if (pdn->busno != bus ||
|
|
pdn->devfn != devfn)
|
|
continue;
|
|
pdn->last_allow_rc = rc;
|
|
}
|
|
}
|
|
} else {
|
|
pdn = pci_get_pdn(edev->pdev);
|
|
physfn_pdn = pci_get_pdn(edev->physfn);
|
|
|
|
vf_pe_num = physfn_pdn->pe_num_map[edev->vf_index];
|
|
vf_pe_array[0] = cpu_to_be16(vf_pe_num);
|
|
rc = pseries_send_allow_unfreeze(physfn_pdn,
|
|
vf_pe_array, 1);
|
|
pdn->last_allow_rc = rc;
|
|
}
|
|
}
|
|
|
|
kfree(vf_pe_array);
|
|
return rc;
|
|
}
|
|
|
|
static int pseries_notify_resume(struct pci_dn *pdn)
|
|
{
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
|
|
|
if (!edev)
|
|
return -EEXIST;
|
|
|
|
if (rtas_token("ibm,open-sriov-allow-unfreeze")
|
|
== RTAS_UNKNOWN_SERVICE)
|
|
return -EINVAL;
|
|
|
|
if (edev->pdev->is_physfn || edev->pdev->is_virtfn)
|
|
return pseries_call_allow_unfreeze(edev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct eeh_ops pseries_eeh_ops = {
|
|
.name = "pseries",
|
|
.init = pseries_eeh_init,
|
|
.probe = pseries_eeh_probe,
|
|
.set_option = pseries_eeh_set_option,
|
|
.get_state = pseries_eeh_get_state,
|
|
.reset = pseries_eeh_reset,
|
|
.get_log = pseries_eeh_get_log,
|
|
.configure_bridge = pseries_eeh_configure_bridge,
|
|
.err_inject = NULL,
|
|
.read_config = pseries_eeh_read_config,
|
|
.write_config = pseries_eeh_write_config,
|
|
.next_error = NULL,
|
|
.restore_config = NULL, /* NB: configure_bridge() does this */
|
|
#ifdef CONFIG_PCI_IOV
|
|
.notify_resume = pseries_notify_resume
|
|
#endif
|
|
};
|
|
|
|
/**
|
|
* eeh_pseries_init - Register platform dependent EEH operations
|
|
*
|
|
* EEH initialization on pseries platform. This function should be
|
|
* called before any EEH related functions.
|
|
*/
|
|
static int __init eeh_pseries_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = eeh_ops_register(&pseries_eeh_ops);
|
|
if (!ret)
|
|
pr_info("EEH: pSeries platform initialized\n");
|
|
else
|
|
pr_info("EEH: pSeries platform initialization failure (%d)\n",
|
|
ret);
|
|
|
|
return ret;
|
|
}
|
|
machine_early_initcall(pseries, eeh_pseries_init);
|