0df9528736
If packet checker is enabled in the serdes, then Rx counter registers start working, and no side effects have been detected. This patch enables packet checker automatically when powering serdes on, and exposes Rx counter registers via ethtool statistics interface. Code partially basded by older attempt by Andrew Lunn. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
655 lines
16 KiB
C
655 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Marvell 88E6xxx SERDES manipulation, via SMI bus
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/mii.h>
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#include "chip.h"
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#include "global2.h"
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#include "phy.h"
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#include "port.h"
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#include "serdes.h"
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static int mv88e6352_serdes_read(struct mv88e6xxx_chip *chip, int reg,
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u16 *val)
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{
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return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES,
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MV88E6352_SERDES_PAGE_FIBER,
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reg, val);
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}
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static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg,
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u16 val)
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{
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return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES,
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MV88E6352_SERDES_PAGE_FIBER,
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reg, val);
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}
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static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip,
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int lane, int device, int reg, u16 *val)
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{
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int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
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return mv88e6xxx_phy_read(chip, lane, reg_c45, val);
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}
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static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip,
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int lane, int device, int reg, u16 val)
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{
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int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
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return mv88e6xxx_phy_write(chip, lane, reg_c45, val);
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}
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int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool up)
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{
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u16 val, new_val;
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int err;
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err = mv88e6352_serdes_read(chip, MII_BMCR, &val);
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if (err)
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return err;
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if (up)
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new_val = val & ~BMCR_PDOWN;
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else
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new_val = val | BMCR_PDOWN;
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if (val != new_val)
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err = mv88e6352_serdes_write(chip, MII_BMCR, new_val);
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return err;
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}
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u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
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{
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u8 cmode = chip->ports[port].cmode;
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u8 lane = 0;
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if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX) ||
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(cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX) ||
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(cmode == MV88E6XXX_PORT_STS_CMODE_SGMII))
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lane = 0xff; /* Unused */
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return lane;
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}
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static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port)
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{
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if (mv88e6xxx_serdes_get_lane(chip, port))
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return true;
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return false;
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}
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struct mv88e6352_serdes_hw_stat {
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char string[ETH_GSTRING_LEN];
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int sizeof_stat;
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int reg;
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};
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static struct mv88e6352_serdes_hw_stat mv88e6352_serdes_hw_stats[] = {
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{ "serdes_fibre_rx_error", 16, 21 },
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{ "serdes_PRBS_error", 32, 24 },
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};
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int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port)
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{
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if (mv88e6352_port_has_serdes(chip, port))
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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return 0;
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}
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int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
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int port, uint8_t *data)
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{
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struct mv88e6352_serdes_hw_stat *stat;
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int i;
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if (!mv88e6352_port_has_serdes(chip, port))
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return 0;
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for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
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stat = &mv88e6352_serdes_hw_stats[i];
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memcpy(data + i * ETH_GSTRING_LEN, stat->string,
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ETH_GSTRING_LEN);
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}
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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}
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static uint64_t mv88e6352_serdes_get_stat(struct mv88e6xxx_chip *chip,
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struct mv88e6352_serdes_hw_stat *stat)
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{
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u64 val = 0;
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u16 reg;
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int err;
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err = mv88e6352_serdes_read(chip, stat->reg, ®);
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if (err) {
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dev_err(chip->dev, "failed to read statistic\n");
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return 0;
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}
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val = reg;
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if (stat->sizeof_stat == 32) {
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err = mv88e6352_serdes_read(chip, stat->reg + 1, ®);
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if (err) {
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dev_err(chip->dev, "failed to read statistic\n");
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return 0;
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}
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val = val << 16 | reg;
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}
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return val;
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}
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int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data)
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{
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struct mv88e6xxx_port *mv88e6xxx_port = &chip->ports[port];
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struct mv88e6352_serdes_hw_stat *stat;
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u64 value;
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int i;
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if (!mv88e6352_port_has_serdes(chip, port))
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return 0;
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BUILD_BUG_ON(ARRAY_SIZE(mv88e6352_serdes_hw_stats) >
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ARRAY_SIZE(mv88e6xxx_port->serdes_stats));
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for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
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stat = &mv88e6352_serdes_hw_stats[i];
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value = mv88e6352_serdes_get_stat(chip, stat);
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mv88e6xxx_port->serdes_stats[i] += value;
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data[i] = mv88e6xxx_port->serdes_stats[i];
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}
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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}
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static void mv88e6352_serdes_irq_link(struct mv88e6xxx_chip *chip, int port)
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{
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struct dsa_switch *ds = chip->ds;
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u16 status;
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bool up;
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int err;
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err = mv88e6352_serdes_read(chip, MII_BMSR, &status);
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if (err)
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return;
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/* Status must be read twice in order to give the current link
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* status. Otherwise the change in link status since the last
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* read of the register is returned.
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*/
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err = mv88e6352_serdes_read(chip, MII_BMSR, &status);
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if (err)
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return;
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up = status & BMSR_LSTATUS;
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dsa_port_phylink_mac_change(ds, port, up);
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}
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irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
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u8 lane)
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{
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irqreturn_t ret = IRQ_NONE;
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u16 status;
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int err;
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err = mv88e6352_serdes_read(chip, MV88E6352_SERDES_INT_STATUS, &status);
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if (err)
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return ret;
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if (status & MV88E6352_SERDES_INT_LINK_CHANGE) {
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ret = IRQ_HANDLED;
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mv88e6352_serdes_irq_link(chip, port);
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}
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return ret;
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}
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int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool enable)
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{
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u16 val = 0;
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if (enable)
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val |= MV88E6352_SERDES_INT_LINK_CHANGE;
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return mv88e6352_serdes_write(chip, MV88E6352_SERDES_INT_ENABLE, val);
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}
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unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
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{
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return irq_find_mapping(chip->g2_irq.domain, MV88E6352_SERDES_IRQ);
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}
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u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
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{
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u8 cmode = chip->ports[port].cmode;
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u8 lane = 0;
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switch (port) {
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case 5:
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if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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lane = MV88E6341_PORT5_LANE;
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break;
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}
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return lane;
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}
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u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
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{
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u8 cmode = chip->ports[port].cmode;
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u8 lane = 0;
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switch (port) {
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case 9:
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if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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lane = MV88E6390_PORT9_LANE0;
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break;
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case 10:
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if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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lane = MV88E6390_PORT10_LANE0;
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break;
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}
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return lane;
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}
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u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
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{
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u8 cmode_port = chip->ports[port].cmode;
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u8 cmode_port10 = chip->ports[10].cmode;
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u8 cmode_port9 = chip->ports[9].cmode;
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u8 lane = 0;
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switch (port) {
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case 2:
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if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT9_LANE1;
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break;
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case 3:
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if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT9_LANE2;
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break;
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case 4:
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if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT9_LANE3;
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break;
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case 5:
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if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT10_LANE1;
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break;
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case 6:
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if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT10_LANE2;
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break;
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case 7:
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if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
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lane = MV88E6390_PORT10_LANE3;
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break;
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case 9:
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if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_XAUI ||
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cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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lane = MV88E6390_PORT9_LANE0;
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break;
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case 10:
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if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_XAUI ||
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cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
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lane = MV88E6390_PORT10_LANE0;
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break;
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}
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return lane;
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}
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/* Set power up/down for 10GBASE-R and 10GBASE-X4/X2 */
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static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, u8 lane,
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bool up)
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{
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u16 val, new_val;
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int err;
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err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_PCS_CONTROL_1, &val);
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if (err)
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return err;
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if (up)
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new_val = val & ~(MV88E6390_PCS_CONTROL_1_RESET |
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MV88E6390_PCS_CONTROL_1_LOOPBACK |
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MV88E6390_PCS_CONTROL_1_PDOWN);
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else
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new_val = val | MV88E6390_PCS_CONTROL_1_PDOWN;
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if (val != new_val)
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err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_PCS_CONTROL_1, new_val);
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return err;
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}
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/* Set power up/down for SGMII and 1000Base-X */
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static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, u8 lane,
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bool up)
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{
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u16 val, new_val;
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int err;
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err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_SGMII_CONTROL, &val);
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if (err)
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return err;
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if (up)
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new_val = val & ~(MV88E6390_SGMII_CONTROL_RESET |
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MV88E6390_SGMII_CONTROL_LOOPBACK |
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MV88E6390_SGMII_CONTROL_PDOWN);
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else
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new_val = val | MV88E6390_SGMII_CONTROL_PDOWN;
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if (val != new_val)
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err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_SGMII_CONTROL, new_val);
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return err;
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}
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struct mv88e6390_serdes_hw_stat {
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char string[ETH_GSTRING_LEN];
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int reg;
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};
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static struct mv88e6390_serdes_hw_stat mv88e6390_serdes_hw_stats[] = {
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{ "serdes_rx_pkts", 0xf021 },
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{ "serdes_rx_bytes", 0xf024 },
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{ "serdes_rx_pkts_error", 0xf027 },
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};
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int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port)
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{
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if (mv88e6390_serdes_get_lane(chip, port) == 0)
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return 0;
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return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
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}
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int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
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int port, uint8_t *data)
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{
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struct mv88e6390_serdes_hw_stat *stat;
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int i;
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if (mv88e6390_serdes_get_lane(chip, port) == 0)
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return 0;
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for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) {
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stat = &mv88e6390_serdes_hw_stats[i];
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memcpy(data + i * ETH_GSTRING_LEN, stat->string,
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ETH_GSTRING_LEN);
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}
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return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
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}
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static uint64_t mv88e6390_serdes_get_stat(struct mv88e6xxx_chip *chip, int lane,
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struct mv88e6390_serdes_hw_stat *stat)
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{
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u16 reg[3];
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int err, i;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
|
|
stat->reg + i, ®[i]);
|
|
if (err) {
|
|
dev_err(chip->dev, "failed to read statistic\n");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return reg[0] | ((u64)reg[1] << 16) | ((u64)reg[2] << 32);
|
|
}
|
|
|
|
int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
|
|
uint64_t *data)
|
|
{
|
|
struct mv88e6390_serdes_hw_stat *stat;
|
|
int lane;
|
|
int i;
|
|
|
|
lane = mv88e6390_serdes_get_lane(chip, port);
|
|
if (lane == 0)
|
|
return 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) {
|
|
stat = &mv88e6390_serdes_hw_stats[i];
|
|
data[i] = mv88e6390_serdes_get_stat(chip, lane, stat);
|
|
}
|
|
|
|
return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
|
|
}
|
|
|
|
static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, u8 lane)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
|
|
MV88E6390_PG_CONTROL, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg |= MV88E6390_PG_CONTROL_ENABLE_PC;
|
|
return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
|
|
MV88E6390_PG_CONTROL, reg);
|
|
}
|
|
|
|
int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
|
|
bool up)
|
|
{
|
|
u8 cmode = chip->ports[port].cmode;
|
|
int err = 0;
|
|
|
|
switch (cmode) {
|
|
case MV88E6XXX_PORT_STS_CMODE_SGMII:
|
|
case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
|
|
case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
|
|
err = mv88e6390_serdes_power_sgmii(chip, lane, up);
|
|
break;
|
|
case MV88E6XXX_PORT_STS_CMODE_XAUI:
|
|
case MV88E6XXX_PORT_STS_CMODE_RXAUI:
|
|
err = mv88e6390_serdes_power_10g(chip, lane, up);
|
|
break;
|
|
}
|
|
|
|
if (!err && up)
|
|
err = mv88e6390_serdes_enable_checker(chip, lane);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mv88e6390_serdes_irq_link_sgmii(struct mv88e6xxx_chip *chip,
|
|
int port, u8 lane)
|
|
{
|
|
u8 cmode = chip->ports[port].cmode;
|
|
struct dsa_switch *ds = chip->ds;
|
|
int duplex = DUPLEX_UNKNOWN;
|
|
int speed = SPEED_UNKNOWN;
|
|
phy_interface_t mode;
|
|
int link, err;
|
|
u16 status;
|
|
|
|
err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
|
|
MV88E6390_SGMII_PHY_STATUS, &status);
|
|
if (err) {
|
|
dev_err(chip->dev, "can't read SGMII PHY status: %d\n", err);
|
|
return;
|
|
}
|
|
|
|
link = status & MV88E6390_SGMII_PHY_STATUS_LINK ?
|
|
LINK_FORCED_UP : LINK_FORCED_DOWN;
|
|
|
|
if (status & MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID) {
|
|
duplex = status & MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL ?
|
|
DUPLEX_FULL : DUPLEX_HALF;
|
|
|
|
switch (status & MV88E6390_SGMII_PHY_STATUS_SPEED_MASK) {
|
|
case MV88E6390_SGMII_PHY_STATUS_SPEED_1000:
|
|
if (cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
|
|
speed = SPEED_2500;
|
|
else
|
|
speed = SPEED_1000;
|
|
break;
|
|
case MV88E6390_SGMII_PHY_STATUS_SPEED_100:
|
|
speed = SPEED_100;
|
|
break;
|
|
case MV88E6390_SGMII_PHY_STATUS_SPEED_10:
|
|
speed = SPEED_10;
|
|
break;
|
|
default:
|
|
dev_err(chip->dev, "invalid PHY speed\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
switch (cmode) {
|
|
case MV88E6XXX_PORT_STS_CMODE_SGMII:
|
|
mode = PHY_INTERFACE_MODE_SGMII;
|
|
break;
|
|
case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
|
|
mode = PHY_INTERFACE_MODE_1000BASEX;
|
|
break;
|
|
case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
|
|
mode = PHY_INTERFACE_MODE_2500BASEX;
|
|
break;
|
|
default:
|
|
mode = PHY_INTERFACE_MODE_NA;
|
|
}
|
|
|
|
err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
|
|
PAUSE_OFF, mode);
|
|
if (err)
|
|
dev_err(chip->dev, "can't propagate PHY settings to MAC: %d\n",
|
|
err);
|
|
else
|
|
dsa_port_phylink_mac_change(ds, port, link == LINK_FORCED_UP);
|
|
}
|
|
|
|
static int mv88e6390_serdes_irq_enable_sgmii(struct mv88e6xxx_chip *chip,
|
|
u8 lane, bool enable)
|
|
{
|
|
u16 val = 0;
|
|
|
|
if (enable)
|
|
val |= MV88E6390_SGMII_INT_LINK_DOWN |
|
|
MV88E6390_SGMII_INT_LINK_UP;
|
|
|
|
return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
|
|
MV88E6390_SGMII_INT_ENABLE, val);
|
|
}
|
|
|
|
int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
|
|
bool enable)
|
|
{
|
|
u8 cmode = chip->ports[port].cmode;
|
|
|
|
switch (cmode) {
|
|
case MV88E6XXX_PORT_STS_CMODE_SGMII:
|
|
case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
|
|
case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
|
|
return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip,
|
|
u8 lane, u16 *status)
|
|
{
|
|
int err;
|
|
|
|
err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
|
|
MV88E6390_SGMII_INT_STATUS, status);
|
|
|
|
return err;
|
|
}
|
|
|
|
irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
|
|
u8 lane)
|
|
{
|
|
u8 cmode = chip->ports[port].cmode;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u16 status;
|
|
int err;
|
|
|
|
switch (cmode) {
|
|
case MV88E6XXX_PORT_STS_CMODE_SGMII:
|
|
case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
|
|
case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
|
|
err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status);
|
|
if (err)
|
|
return ret;
|
|
if (status & (MV88E6390_SGMII_INT_LINK_DOWN |
|
|
MV88E6390_SGMII_INT_LINK_UP)) {
|
|
ret = IRQ_HANDLED;
|
|
mv88e6390_serdes_irq_link_sgmii(chip, port, lane);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
return irq_find_mapping(chip->g2_irq.domain, port);
|
|
}
|