Diogo Ivo 23a43cc437 clk: tegra: Add missing reset deassertion ... Commit 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. Fix this problem by adding explicit deassert/assert requests to the driver. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes: 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>		2022-05-04 11:21:16 +02:00
..
clk-audio-sync.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-bpmp.c	clk: tegra: bpmp: Clamp clock rates on requests	2020-11-26 16:28:07 +01:00
clk-device.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-dfll.c	clk: tegra: Add missing reset deassertion	2022-05-04 11:21:16 +02:00
clk-dfll.h	clk: tegra: clk-dfll: Add suspend and resume support	2019-11-11 14:53:03 +01:00
clk-divider.c	clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation	2020-01-10 15:50:05 +01:00
clk-id.h	clk: tegra: Fix duplicated SE clock entry	2020-12-10 12:51:59 -08:00
clk-periph-fixed.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-periph-gate.c	clk: tegra: Don't deassert reset on enabling clocks	2021-05-31 15:16:46 +02:00
clk-periph.c	clk: tegra: Fix refcounting of gate clocks	2021-05-31 15:16:24 +02:00
clk-pll-out.c	clk: tegra: pllout: Save and restore pllout context	2019-11-11 14:53:02 +01:00
clk-pll.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-sdmmc-mux.c	clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops	2021-07-27 14:54:19 -07:00
clk-super.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-tegra20-emc.c	clk: tegra: Export Tegra20 EMC kernel symbols	2020-11-06 19:24:04 +01:00
clk-tegra20.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-tegra30.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-tegra114.c	clk: tegra: Make vde a child of pll_p on tegra114	2021-12-15 16:39:15 +01:00
clk-tegra124-dfll-fcpu.c	clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator	2021-06-25 16:23:07 -07:00
clk-tegra124-emc.c	clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver	2022-03-11 19:22:18 -08:00
clk-tegra124.c	memory: tegra124-emc: Make driver modular	2021-01-05 18:00:09 +01:00
clk-tegra210-emc.c	This pull request contains zero diff to the core framework. It is a collection	2020-10-22 12:53:28 -07:00
clk-tegra210.c	clk: tegra: Add PLLE HW power sequencer control	2021-03-24 14:01:58 +01:00
clk-tegra-audio.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c	clk: tegra: Remove CLK_M_DIV fixed clocks	2020-03-12 11:33:32 +01:00
clk-tegra-periph.c	clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock	2021-08-11 11:57:01 +02:00
clk-tegra-super-cclk.c	clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling	2021-05-31 15:16:26 +02:00
clk-tegra-super-gen4.c	clk: tegra: clk-super: Fix to enable PLLP branches to CPU	2019-11-11 14:53:03 +01:00
clk-utils.c	clk: tegra: Refactor fractional divider calculation	2018-07-25 13:43:34 -07:00
clk.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk.h	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
cvb.c	clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param	2021-02-11 11:56:05 -08:00
cvb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
Kconfig	memory: tegra124-emc: Make driver modular	2021-01-05 18:00:09 +01:00
Makefile	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00