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Arnd Bergmann 267511c977 Renesas RISC-V defconfig updates for v6.2

- Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK
     board in the risc-v defconfig.
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Merge tag 'renesas-riscv-defconfig-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig

Renesas RISC-V defconfig updates for v6.2

  - Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK
    board in the risc-v defconfig.

* tag 'renesas-riscv-defconfig-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  riscv: configs: defconfig: Enable Renesas RZ/Five SoC

Link: https://lore.kernel.org/r/cover.1668788928.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

2022-11-21 10:49:41 +01:00

boot

RISC-V Patches for the 6.1 Merge Window, Part 2

2022-10-14 11:21:11 -07:00

configs

riscv: configs: defconfig: Enable Renesas RZ/Five SoC

2022-11-10 16:37:58 +01:00

errata

Merge patch series "Some style cleanups for recent extension additions"

2022-10-13 08:46:31 -07:00

include

RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc