Paul Cercueil 268db077ac clk: ingenic: support PLLs with no bypass bit ... The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18479/ Signed-off-by: James Hogan <jhogan@kernel.org>		2018-01-18 22:05:13 +00:00
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cgu.c	clk: ingenic: support PLLs with no bypass bit	2018-01-18 22:05:13 +00:00
cgu.h	clk: ingenic: support PLLs with no bypass bit	2018-01-18 22:05:13 +00:00
jz4740-cgu.c	Update MIPS email addresses	2017-11-03 09:02:30 -07:00
jz4780-cgu.c	clk: ingenic: Use const pointer to clk_ops in struct	2018-01-18 22:04:36 +00:00
Makefile	clk: ingenic: add JZ4780 CGU support	2015-06-21 21:53:20 +02:00