26e6d50e93
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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.. | ||
Kconfig | ||
Makefile | ||
phy-ath79-usb.c | ||
phy-qcom-apq8064-sata.c | ||
phy-qcom-ipq806x-sata.c | ||
phy-qcom-ipq806x-usb.c | ||
phy-qcom-ipq4019-usb.c | ||
phy-qcom-pcie2.c | ||
phy-qcom-qmp.c | ||
phy-qcom-qmp.h | ||
phy-qcom-qusb2.c | ||
phy-qcom-snps-femto-v2.c | ||
phy-qcom-usb-hs-28nm.c | ||
phy-qcom-usb-hs.c | ||
phy-qcom-usb-hsic.c | ||
phy-qcom-usb-ss.c |