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Like Xu 27461da310 KVM: x86/pmu: Support full width counting

Intel CPUs have a new alternative MSR range (starting from MSR_IA32_PMC0)
for GP counters that allows writing the full counter width. Enable this
range from a new capability bit (IA32_PERF_CAPABILITIES.FW_WRITE[bit 13]).

The guest would query CPUID to get the counter width, and sign extends
the counter values as needed. The traditional MSRs always limit to 32bit,
even though the counter internally is larger (48 or 57 bits).

When the new capability is set, use the alternative range which do not
have these restrictions. This lowers the overhead of perf stat slightly
because it has to do less interrupts to accumulate the counter value.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20200529074347.124619-3-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2020-06-01 04:26:09 -04:00

capabilities.h

KVM: x86/pmu: Support full width counting

2020-06-01 04:26:09 -04:00

evmcs.c

KVM: eVMCS: check if nesting is enabled

2020-04-23 09:04:56 -04:00

evmcs.h

KVM: nVMX: properly handle errors in nested_vmx_handle_enlightened_vmptrld()

2020-03-16 18:19:30 +01:00

nested.c

KVM: x86: extend struct kvm_vcpu_pv_apf_data with token info