fea84890e5
Add a new function to configure the shared clock between two i2s ports, and export it. This will allow the clock sharing to be set from the machine driver instead of the devicetree. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220908161154.648557-5-nfraprado@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
112 lines
2.3 KiB
C
112 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8183-afe-common.h -- Mediatek 8183 audio driver definitions
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*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
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*/
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#ifndef _MT_8183_AFE_COMMON_H_
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#define _MT_8183_AFE_COMMON_H_
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#include <sound/soc.h>
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include "../common/mtk-base-afe.h"
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enum {
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MT8183_MEMIF_DL1,
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MT8183_MEMIF_DL2,
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MT8183_MEMIF_DL3,
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MT8183_MEMIF_VUL12,
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MT8183_MEMIF_VUL2,
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MT8183_MEMIF_AWB,
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MT8183_MEMIF_AWB2,
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MT8183_MEMIF_MOD_DAI,
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MT8183_MEMIF_HDMI,
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MT8183_MEMIF_NUM,
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MT8183_DAI_ADDA = MT8183_MEMIF_NUM,
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MT8183_DAI_PCM_1,
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MT8183_DAI_PCM_2,
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MT8183_DAI_I2S_0,
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MT8183_DAI_I2S_1,
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MT8183_DAI_I2S_2,
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MT8183_DAI_I2S_3,
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MT8183_DAI_I2S_5,
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MT8183_DAI_TDM,
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MT8183_DAI_HOSTLESS_LPBK,
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MT8183_DAI_HOSTLESS_SPEECH,
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MT8183_DAI_NUM,
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};
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enum {
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MT8183_IRQ_0,
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MT8183_IRQ_1,
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MT8183_IRQ_2,
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MT8183_IRQ_3,
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MT8183_IRQ_4,
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MT8183_IRQ_5,
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MT8183_IRQ_6,
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MT8183_IRQ_7,
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MT8183_IRQ_8, /* hw bundle to TDM */
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MT8183_IRQ_11,
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MT8183_IRQ_12,
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MT8183_IRQ_NUM,
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};
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enum {
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MT8183_MTKAIF_PROTOCOL_1 = 0,
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MT8183_MTKAIF_PROTOCOL_2,
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MT8183_MTKAIF_PROTOCOL_2_CLK_P2,
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};
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/* MCLK */
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enum {
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MT8183_I2S0_MCK = 0,
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MT8183_I2S1_MCK,
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MT8183_I2S2_MCK,
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MT8183_I2S3_MCK,
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MT8183_I2S4_MCK,
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MT8183_I2S4_BCK,
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MT8183_I2S5_MCK,
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MT8183_MCK_NUM,
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};
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struct clk;
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struct mt8183_afe_private {
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struct clk **clk;
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int pm_runtime_bypass_reg_ctl;
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/* dai */
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void *dai_priv[MT8183_DAI_NUM];
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/* adda */
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int mtkaif_protocol;
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int mtkaif_calibration_ok;
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int mtkaif_chosen_phase[4];
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int mtkaif_phase_cycle[4];
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int mtkaif_calibration_num_phase;
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int mtkaif_dmic;
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/* mck */
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int mck_rate[MT8183_MCK_NUM];
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};
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unsigned int mt8183_general_rate_transform(struct device *dev,
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unsigned int rate);
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unsigned int mt8183_rate_transform(struct device *dev,
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unsigned int rate, int aud_blk);
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int mt8183_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
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const char *secondary_i2s_name);
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/* dai register */
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int mt8183_dai_adda_register(struct mtk_base_afe *afe);
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int mt8183_dai_pcm_register(struct mtk_base_afe *afe);
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int mt8183_dai_i2s_register(struct mtk_base_afe *afe);
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int mt8183_dai_tdm_register(struct mtk_base_afe *afe);
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int mt8183_dai_hostless_register(struct mtk_base_afe *afe);
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#endif
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