28cfea989d
net/mlx5: Support 4 ports VF LAG, part 1/2 This series continues the series[1] "Support 4 ports HCAs LAG mode" by Mark Bloch. This series adds support for 4 ports VF LAG (single FDB E-Switch). This series of patches focuses on refactoring different sections of the code that make assumptions about VF LAG supporting only two ports. For instance, it assumes that each device can only have one peer. Patches 1-5: - Refactor ETH handling of TC rules of eswitches with peers. Patch 6: - Refactors peer miss group table. Patches 7-9: - Refactor single FDB E-Switch creation. Patch 10: - Refactor the DR layer. Patches 11-14: - Refactors devcom layer. Next series will refactor LAG layer and enable 4 ports VF LAG. This series specifically allows HCAs with 4 ports to create a VF LAG with only 4 ports. It is not possible to create a VF LAG with 2 or 3 ports using HCAs that have 4 ports. Currently, the Merged E-Switch feature only supports HCAs with 2 ports. However, upcoming patches will introduce support for HCAs with 4 ports. In order to activate VF LAG a user can execute: devlink dev eswitch set pci/0000:08:00.0 mode switchdev devlink dev eswitch set pci/0000:08:00.1 mode switchdev devlink dev eswitch set pci/0000:08:00.2 mode switchdev devlink dev eswitch set pci/0000:08:00.3 mode switchdev ip link add name bond0 type bond ip link set dev bond0 type bond mode 802.3ad ip link set dev eth2 master bond0 ip link set dev eth3 master bond0 ip link set dev eth4 master bond0 ip link set dev eth5 master bond0 Where eth2, eth3, eth4 and eth5 are net-interfaces of pci/0000:08:00.0 pci/0000:08:00.1 pci/0000:08:00.2 pci/0000:08:00.3 respectively. User can verify LAG state and type via debugfs: /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/state /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/type [1] https://lore.kernel.org/netdev/20220510055743.118828-1-saeedm@nvidia.com/ -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAmR6PrkACgkQSD+KveBX +j4QYAf/TlwnjQP+Is+9lJEIC+RH1bDPEsbiw+kwlMU6AveDYaHl1bevjJoE7qS5 uvVunRh7SENWtU56TOiYO7CwkbTHAx1WdJdXZDudfed1olF0hMUO5yDixaFgiCMn hTWJJvNprWWK5Ti+yZ39ZHsrigXze7g4ZoJ0JFyDKfR3cobqNjgpOLXz+XMR0NEY 7ym6VxZATNjVWorBeHMA+Oe249s4oK/m5i0LV/8yrkhDpFkCcfkTdLmvKQ+TRu11 Akq1dd236LqGqAPO2tFg8NgnjsXu1vvCJnvjML5VFDbruDv3h3fa6F0mClrRmYm7 f7I32QW10+NYBANcoWVCn6EQzmWDpQ== =ZDar -----END PGP SIGNATURE----- Merge tag 'mlx5-updates-2023-05-31' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-updates-2023-05-31 net/mlx5: Support 4 ports VF LAG, part 1/2 This series continues the series[1] "Support 4 ports HCAs LAG mode" by Mark Bloch. This series adds support for 4 ports VF LAG (single FDB E-Switch). This series of patches focuses on refactoring different sections of the code that make assumptions about VF LAG supporting only two ports. For instance, it assumes that each device can only have one peer. Patches 1-5: - Refactor ETH handling of TC rules of eswitches with peers. Patch 6: - Refactors peer miss group table. Patches 7-9: - Refactor single FDB E-Switch creation. Patch 10: - Refactor the DR layer. Patches 11-14: - Refactors devcom layer. Next series will refactor LAG layer and enable 4 ports VF LAG. This series specifically allows HCAs with 4 ports to create a VF LAG with only 4 ports. It is not possible to create a VF LAG with 2 or 3 ports using HCAs that have 4 ports. Currently, the Merged E-Switch feature only supports HCAs with 2 ports. However, upcoming patches will introduce support for HCAs with 4 ports. In order to activate VF LAG a user can execute: devlink dev eswitch set pci/0000:08:00.0 mode switchdev devlink dev eswitch set pci/0000:08:00.1 mode switchdev devlink dev eswitch set pci/0000:08:00.2 mode switchdev devlink dev eswitch set pci/0000:08:00.3 mode switchdev ip link add name bond0 type bond ip link set dev bond0 type bond mode 802.3ad ip link set dev eth2 master bond0 ip link set dev eth3 master bond0 ip link set dev eth4 master bond0 ip link set dev eth5 master bond0 Where eth2, eth3, eth4 and eth5 are net-interfaces of pci/0000:08:00.0 pci/0000:08:00.1 pci/0000:08:00.2 pci/0000:08:00.3 respectively. User can verify LAG state and type via debugfs: /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/state /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/type [1] https://lore.kernel.org/netdev/20220510055743.118828-1-saeedm@nvidia.com/ * tag 'mlx5-updates-2023-05-31' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5: Devcom, extend mlx5_devcom_send_event to work with more than two devices net/mlx5: Devcom, introduce devcom_for_each_peer_entry net/mlx5: E-switch, mark devcom as not ready when all eswitches are unpaired net/mlx5: Devcom, Rename paired to ready net/mlx5: DR, handle more than one peer domain net/mlx5: E-switch, generalize shared FDB creation net/mlx5: E-switch, Handle multiple master egress rules net/mlx5: E-switch, refactor FDB miss rule add/remove net/mlx5: E-switch, enlarge peer miss group table net/mlx5e: Handle offloads flows per peer net/mlx5e: en_tc, re-factor query route port net/mlx5e: rep, store send to vport rules per peer net/mlx5e: tc, Refactor peer add/del flow net/mlx5e: en_tc, Extend peer flows to a list ==================== Link: https://lore.kernel.org/r/20230602191301.47004-1-saeed@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.