Leo (Hanghong) Ma 28fa24ad14 drm/amd/display: Change the delay time before enabling FEC
[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.

[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173 us. So using 7 microseconds delay instead of
1 miliseconds.

Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05 18:18:33 -05:00
..
2019-11-14 05:53:10 +10:00
2019-08-14 18:31:10 +02:00
2019-11-14 05:53:10 +10:00
2019-10-24 17:59:45 +02:00
2019-10-04 17:04:05 +01:00
2019-10-03 16:38:50 +02:00
2019-09-19 16:24:24 -07:00
2019-06-30 09:48:05 +02:00
2019-10-23 12:10:05 +02:00
2019-11-14 05:53:10 +10:00
2019-07-17 12:52:55 +02:00
2019-06-05 20:31:04 +02:00
2019-07-15 18:11:31 +02:00
2019-06-05 20:29:57 +02:00
2019-09-16 15:14:43 +02:00
2019-07-17 12:52:55 +02:00
2019-10-11 09:30:53 +10:00
2019-11-14 05:53:10 +10:00
2019-10-23 11:14:11 -04:00
2019-07-22 21:24:10 +02:00
2019-11-14 05:53:10 +10:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-10-08 18:29:00 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-11-15 08:00:08 +01:00
2019-05-27 18:07:03 +02:00
2019-07-22 21:24:10 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-09-19 16:24:24 -07:00
2019-05-27 18:07:03 +02:00
2019-10-02 16:28:55 +03:00
2019-05-27 18:07:03 +02:00
2019-10-03 16:38:50 +02:00