2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/asm-mips/dec/kn02ca.h
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*
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* Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
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*
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* Copyright (C) 2002, 2003 Maciej W. Rozycki
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*/
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#ifndef __ASM_MIPS_DEC_KN02CA_H
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#define __ASM_MIPS_DEC_KN02CA_H
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#include <asm/dec/kn02xa.h> /* For common definitions. */
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/*
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* CPU interrupt bits.
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*/
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#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */
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#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
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#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */
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#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */
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#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */
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/*
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* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
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*/
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#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */
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#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
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#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
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#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */
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#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */
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#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */
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#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
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#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
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#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
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#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */
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#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
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#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */
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#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */
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#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */
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#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */
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#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */
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#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */
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/*
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* Memory Error Register bits.
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*/
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#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */
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/*
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* Memory Size Register bits.
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*/
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#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */
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#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */
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#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */
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#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */
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#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */
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/*
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* I/O ASIC System Support Register bits.
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*/
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#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */
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#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */
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#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
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#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
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#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
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#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
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#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
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#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
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#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */
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#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */
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#define KN03CA_IO_SSR_LED (1<<0) /* power LED */
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#endif /* __ASM_MIPS_DEC_KN02CA_H */
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