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The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS
API for the calculation.
Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>
2aba76f014