d7d456a520
Add bindings for the reset controller on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
39 lines
693 B
YAML
39 lines
693 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7100 SoC Reset Controller Device Tree Bindings
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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enum:
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- starfive,jh7100-reset
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reg:
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maxItems: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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reset-controller@11840000 {
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compatible = "starfive,jh7100-reset";
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reg = <0x11840000 0x10000>;
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#reset-cells = <1>;
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};
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...
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