linux

iv/linux

History

Greg Kroah-Hartman 2e4a4e3628 cacheinfo and arch_topology updates for v6.3

The main change is to build the cache topology information for all
 the CPUs from the primary CPU. Currently the cacheinfo for secondary CPUs
 is created during the early boot on the respective CPU itself. Preemption
 and interrupts are disabled at this stage. On PREEMPT_RT kernels, allocating
 memory and even parsing the PPTT table for ACPI based systems triggers a:
   'BUG: sleeping function called from invalid context'
 
 To prevent this bug, the cacheinfo is now allocated from the primary CPU
 when preemption and interrupts are enabled and before booting secondary
 CPUs. The cache levels/leaves are computed from DT/ACPI PPTT information
 only, without relying on any architecture specific mechanism if done so
 early.
 
 The other minor change included here is to handle shared caches at
 different levels when not all the CPUs on the system have the same
 cache hierarchy.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmPKg60ACgkQAEG6vDF+
 4pi91hAAoSluqjbUHzzCW+OIIjKAAvQrAw6bsKGvSpcUfYno1Lry+9y76L6TMYSy
 OPtiKGxcJyzhdlCwIpJzgaX9nTz7uiu70euNZiAp11XA2KlphtLoI3TMUa60jD4i
 ZGfn9UiAp719Vog5m3CmZXjHZ6drI0HloL8ZWTl4VDATUu5pfcx4uYPT2o63Xc62
 k5QglaRJWFhFAJ+R6R9vQS2zfeMI9xvehl72445wb8pxxPW2f91dvBhJqJgKlziw
 gHKx+D1DnpAUd+v+7HAEmzjXKlY6JnQybmBHmRayllVAa8kGUtvhTcBlRGNsNBzR
 m7VBFKq+eSk7VgxOgka1qXVtHUrlaEWf5qWnG+w4XEiE1VgzNagjaFRaGQQneKI/
 z3yNKG8Xjp+3BdSz0pUDJVEWFnnjueAUEh6/xODEXnWdX166abQZslLIHCvmcnM8
 q7blasuj2mxyCZFC1tyK9WHI7/KCe0cmHbdau3qs0j9bvhzfdB3DwMLsdRjXQTOv
 8FVX0Z5EKY9/bW2oqCg/mb3KOWbmFX2ZHho4cds3IV+9GGB8JkD/6b8vpGejmmx2
 E2vInzhP3gLd9WiWQWDjg4+aklE29P/nDAA8BSPnW3TtEGAFJMZZQRgNlCZnBW56
 Tx2/lE0VD5/UX+1MqSFGchi+KEX3mcZykcra9VNt+uZH26a8gBE=
 =nH4b
 -----END PGP SIGNATURE-----

Merge tag 'archtopo-cacheinfo-updates-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into driver-core-next

Sudeep writes:
  "cacheinfo and arch_topology updates for v6.3

   The main change is to build the cache topology information for all
   the CPUs from the primary CPU. Currently the cacheinfo for secondary CPUs
   is created during the early boot on the respective CPU itself. Preemption
   and interrupts are disabled at this stage. On PREEMPT_RT kernels, allocating
   memory and even parsing the PPTT table for ACPI based systems triggers a:
     'BUG: sleeping function called from invalid context'

   To prevent this bug, the cacheinfo is now allocated from the primary CPU
   when preemption and interrupts are enabled and before booting secondary
   CPUs. The cache levels/leaves are computed from DT/ACPI PPTT information
   only, without relying on any architecture specific mechanism if done so
   early.

   The other minor change included here is to handle shared caches at
   different levels when not all the CPUs on the system have the same
   cache hierarchy."

* tag 'archtopo-cacheinfo-updates-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  cacheinfo: Fix shared_cpu_map to handle shared caches at different levels
  arch_topology: Build cacheinfo from primary CPU
  ACPI: PPTT: Update acpi_find_last_cache_level() to acpi_get_cache_info()
  ACPI: PPTT: Remove acpi_find_cache_levels()
  cacheinfo: Check 'cache-unified' property to count cache leaves
  cacheinfo: Return error code in init_of_cache_level()
  cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation

2023-01-20 13:40:04 +01:00

boot

RISC-V Patches for the 6.2 Merge Window, Part 1

2022-12-14 15:23:49 -08:00

configs

RISC-V Patches for the 6.2 Merge Window, Part 1

2022-12-14 15:23:49 -08:00

errata

drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores

2022-10-27 14:35:20 -07:00

include

riscv: uaccess: fix type of 0 variable on error in get_user()