2ed4fa9cb8
Add support for extended length of read and write transactions. New FPGA logic allows to increase size of the read and write transactions length. This feature is verified through capability register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for length capability detection. Value '10' indicates support of extended transaction length - 128 bytes for read transactions and 132 for write transactions. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Signed-off-by: Wolfram Sang <wsa@kernel.org> |
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.. | ||
algos | ||
busses | ||
muxes | ||
i2c-boardinfo.c | ||
i2c-core-acpi.c | ||
i2c-core-base.c | ||
i2c-core-of.c | ||
i2c-core-slave.c | ||
i2c-core-smbus.c | ||
i2c-core.h | ||
i2c-dev.c | ||
i2c-mux.c | ||
i2c-slave-eeprom.c | ||
i2c-slave-testunit.c | ||
i2c-smbus.c | ||
i2c-stub.c | ||
Kconfig | ||
Makefile |