Dmitry Osipenko a1fdd107cd usb: chipidea: tegra: Specify TX FIFO threshold in UDC SoC info
The UDC/OTG controller could be switched to a host mode and the
TXFILLTUNING register needs to be programmed properly for the host
mode. Hence specify the TX FIFO threshold in the UDC SoC info.

Acked-by: Peter Chen <peter.chen@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201218120246.7759-8-digetx@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-13 11:26:34 +01:00
..
2021-01-13 11:26:34 +01:00
2021-01-13 11:26:34 +01:00
2018-07-05 14:22:47 +08:00