Yixun Lan 2fa9b361e5 clk: meson: axg: fix the od shift of the sys_pll
According to the datasheet, the od shift of sys_pll is actually 16.

Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12 09:49:23 +01:00
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