2ef4e45d99
Errata: The ptp_clock_hi rollsover to zero one clock cycle before it reaches one second boundary. As a result, the pps threshold comparison fails after one second and the pps output signal won't toggle further. This patch workarounds the issue by programming the pps_lo_incr register to 500msec minus one clock cycle period, ensuring that the pps threshold comparison succeeds at one second rollover boundary and pps edge toggles. After that point, the driver will have enough time (~500msec) to reset the pps threshold value. After each one second boundary, hrtimer is invoked which resets the pps threshold value. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Rakesh Babu Saladi <rsaladi2@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
33 lines
612 B
C
33 lines
612 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell PTP driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef PTP_H
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#define PTP_H
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#include <linux/timecounter.h>
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#include <linux/time64.h>
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#include <linux/spinlock.h>
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struct ptp {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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u64 (*read_ptp_tstmp)(struct ptp *ptp);
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spinlock_t ptp_lock; /* lock */
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struct hrtimer hrtimer;
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ktime_t last_ts;
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u32 clock_rate;
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u32 clock_period;
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};
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struct ptp *ptp_get(void);
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void ptp_put(struct ptp *ptp);
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void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts);
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extern struct pci_driver ptp_driver;
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#endif
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