30b842889e
This adds support for the spear13xx platform, which has first been under
review a long time ago and finally been completed after generic spear
work has gone into the clock, dt and pinctrl branches.
Also a number of updates for the samsung socs are part of this branch.
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
"This adds support for the spear13xx platform, which has first been
under review a long time ago and finally been completed after generic
spear work has gone into the clock, dt and pinctrl branches.
Also a number of updates for the samsung socs are part of this branch."
Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d687 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c9836c ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.
So the conflict diff looks like hell, but it's actually a fairly simple
change.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
ARM: exynos: fix building with CONFIG_OF disabled
ARM: EXYNOS: Add AUXDATA for i2c controllers
ARM: dts: Update device tree source files for EXYNOS5250
ARM: EXYNOS: Add device tree support for interrupt combiner
ARM: EXYNOS: Add irq_domain support for interrupt combiner
ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
ARM: EXYNOS: update irqs for EXYNOS5250 SoC
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
ARM: EXYNOS: add GPC4 bank instance
ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
ARM: EXYNOS: Modify the GIC physical address for static io-mapping
ARM: EXYNOS: Add watchdog timer clock instance
pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
SPEAr: Update MAINTAINERS and Documentation
SPEAr13xx: Add defconfig
SPEAr13xx: Add compilation support
SPEAr13xx: Add dts and dtsi files
pinctrl: Add SPEAr13xx pinctrl drivers
pinctrl: SPEAr: Create macro for declaring GPIO PINS
SPEAr13xx: Add common clock framework support
...
233 lines
9.7 KiB
C
233 lines
9.7 KiB
C
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - Power management unit definition
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_PMU_H
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#define __ASM_ARCH_REGS_PMU_H __FILE__
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#include <mach/map.h>
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#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
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#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
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#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
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#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
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#define S5P_USE_STANDBY_WFI0 (1 << 16)
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#define S5P_USE_STANDBY_WFI1 (1 << 17)
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#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
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#define S5P_USE_STANDBY_WFE0 (1 << 24)
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#define S5P_USE_STANDBY_WFE1 (1 << 25)
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#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
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#define S5P_SWRESET S5P_PMUREG(0x0400)
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#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
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#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
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#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
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#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
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#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
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#define S5P_HDMI_PHY_ENABLE (1 << 0)
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#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
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#define S5P_DAC_PHY_ENABLE (1 << 0)
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#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
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#define S5P_MIPI_DPHY_ENABLE (1 << 0)
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#define S5P_MIPI_DPHY_SRESETN (1 << 1)
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#define S5P_MIPI_DPHY_MRESETN (1 << 2)
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#define S5P_INFORM0 S5P_PMUREG(0x0800)
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#define S5P_INFORM1 S5P_PMUREG(0x0804)
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#define S5P_INFORM2 S5P_PMUREG(0x0808)
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#define S5P_INFORM3 S5P_PMUREG(0x080C)
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#define S5P_INFORM4 S5P_PMUREG(0x0810)
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#define S5P_INFORM5 S5P_PMUREG(0x0814)
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#define S5P_INFORM6 S5P_PMUREG(0x0818)
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#define S5P_INFORM7 S5P_PMUREG(0x081C)
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#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
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#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
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#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
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#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
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#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
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#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
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#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
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#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
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#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
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#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
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#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
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#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
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#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
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#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
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#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
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#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
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#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
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#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
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#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
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#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
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#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
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#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
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#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
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#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
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#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
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#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
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#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
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#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
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#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
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#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
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#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
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#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
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#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
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#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
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#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
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#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
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#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
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#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
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#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
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#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
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#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
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#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
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#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
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#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
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#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
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#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
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#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
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#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
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#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
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#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
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#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
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#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
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#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
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#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
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#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
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#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
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#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
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#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
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#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
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#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
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#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
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#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
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#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
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#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
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#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
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#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
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#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
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#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
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#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
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#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
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#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
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#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
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#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
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#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
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#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
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#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
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#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
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#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
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#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
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#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
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#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
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#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
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#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
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#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
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#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
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#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
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#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
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#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
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#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
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#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
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#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
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#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
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#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
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#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
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#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
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#define S5P_CORE_LOCAL_PWR_EN 0x3
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#define S5P_INT_LOCAL_PWR_EN 0x7
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#define S5P_CHECK_SLEEP 0x00000BAD
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/* Only for EXYNOS4210 */
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#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704)
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#define S5P_USBDEVICE_PHY_ENABLE (1 << 0)
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#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
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#define S5P_USBHOST_PHY_ENABLE (1 << 0)
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#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
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#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
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#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
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#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
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#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
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#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
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#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
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#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
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/* Only for EXYNOS4x12 */
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#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
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#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
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#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
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#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
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#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
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#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
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#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
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#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
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#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
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#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
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#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
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#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
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#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
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#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
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#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
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#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
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#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
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#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
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#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
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#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
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#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
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#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
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#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
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#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
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#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
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#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
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#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
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#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
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#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
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#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
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#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
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#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
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#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
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#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
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#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
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#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
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#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
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#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
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/* Only for EXYNOS4412 */
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#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
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#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
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#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
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#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
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#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
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#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
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#endif /* __ASM_ARCH_REGS_PMU_H */
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