Atish Patra 31738ede9b RISC-V: Issue a local tlbflush if possible. ...

In RISC-V, tlb flush happens via SBI which is expensive. If the local
cpu is the only cpu in cpumask, there is no need to invoke a SBI call.

Just do a local flush and return.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

2019-10-29 11:32:18 -07:00

..

boot

riscv: dts: HiFive Unleashed: add default chosen/stdout-path

2019-10-14 12:30:30 -07:00

configs

RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig

2019-09-19 05:44:35 -07:00

include

RISC-V: Add PCIe I/O BAR memory mapping

2019-10-28 10:43:32 -07:00

kernel

riscv: for C functions called only from assembly, mark with __visible

2019-10-28 00:46:02 -07:00

lib

riscv: Using CSR numbers to access CSRs

2019-08-30 11:04:19 -07:00

mm

RISC-V: Issue a local tlbflush if possible.

2019-10-29 11:32:18 -07:00

net

bpf, riscv: Enable zext optimization for more RV64G ALU ops

2019-07-05 23:55:41 +02:00

Kbuild

riscv: add arch/riscv/Kbuild

2019-08-30 17:34:00 -07:00

Kconfig

riscv: make mmap allocation top-down by default

2019-09-24 15:54:12 -07:00

Kconfig.debug

RISC-V: Remove EARLY_PRINTK support

2018-12-17 10:23:46 -08:00

Kconfig.socs

riscv: select SiFive platform drivers with SOC_SIFIVE

2019-07-01 13:20:01 -07:00

Makefile

Kbuild updates for v5.4

2019-09-20 08:36:47 -07:00