f1403342eb
The whole approach wasn't thought through till the end. We already had a reset lock like this in the past and it caused the same problems like this one. Completely revert the patch for now and add individual trylock protection to the hardware access functions as necessary. This reverts commit df9c8d1aa278c435c30a69b8f2418b4a52fcb929. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_XGMI_H__
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#define __AMDGPU_XGMI_H__
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#include <drm/task_barrier.h>
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#include "amdgpu_psp.h"
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struct amdgpu_hive_info {
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uint64_t hive_id;
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struct list_head device_list;
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int number_devices;
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struct mutex hive_lock, reset_lock;
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struct kobject *kobj;
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struct device_attribute dev_attr;
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struct amdgpu_device *adev;
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int hi_req_count;
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struct amdgpu_device *hi_req_gpu;
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struct task_barrier tb;
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enum {
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AMDGPU_XGMI_PSTATE_MIN,
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AMDGPU_XGMI_PSTATE_MAX_VEGA20,
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AMDGPU_XGMI_PSTATE_UNKNOWN
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} pstate;
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};
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struct amdgpu_pcs_ras_field {
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const char *err_name;
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uint32_t pcs_err_mask;
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uint32_t pcs_err_shift;
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};
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struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
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int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
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int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
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void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
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uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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uint64_t addr);
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int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status);
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void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev);
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static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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struct amdgpu_device *bo_adev)
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{
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return (adev != bo_adev &&
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adev->gmc.xgmi.hive_id &&
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adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
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}
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#endif
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