Palmer Dabbelt 32c81bced3 RISC-V: Preliminary Perf Support ... The RISC-V ISA defines a core set of performance counters that must exist on all processors along with a standard way to add more performance counters. This patch set adds preliminary perf support for RISC-V systems. Long term we'll move to model where all PMUs can be built into the kernel at the same time, detected at runtime (possibly via device tree), and provided to userspace. Since we currently only support the ISA-mandated performance counters there's no need to detect anything right now. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-06-04 14:03:18 -07:00
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configs	RISC-V: Enable module support in defconfig	2018-04-02 20:00:56 -07:00
include	perf: riscv: preliminary RISC-V support	2018-06-04 14:02:01 -07:00
kernel	perf: riscv: preliminary RISC-V support	2018-06-04 14:02:01 -07:00
lib	riscv: Fix the bug in memory access fixup code	2018-06-04 13:33:31 -07:00
mm	RISC-V changes for 4.16	2018-02-07 11:33:08 -08:00
Kconfig	perf: riscv: preliminary RISC-V support	2018-06-04 14:02:01 -07:00
Makefile	RISC-V: Fixes to module loading	2018-04-02 20:43:14 -07:00