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linux/arch/riscv/include/asm
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Mark Rutland 33e42ef571 locking/atomic, riscv: Fix atomic64_sub_if_positive() offset argument 
Presently the riscv implementation of atomic64_sub_if_positive() takes
a 32-bit offset value rather than a 64-bit offset value as it should do.
Thus, if called with a 64-bit offset, the value will be unexpectedly
truncated to 32 bits.

Fix this by taking the offset as a long rather than an int.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: arnd@arndb.de
Cc: bp@alien8.de
Cc: catalin.marinas@arm.com
Cc: davem@davemloft.net
Cc: fenghua.yu@intel.com
Cc: heiko.carstens@de.ibm.com
Cc: herbert@gondor.apana.org.au
Cc: ink@jurassic.park.msu.ru
Cc: jhogan@kernel.org
Cc: linux@armlinux.org.uk
Cc: mattst88@gmail.com
Cc: mpe@ellerman.id.au
Cc: paul.burton@mips.com
Cc: paulus@samba.org
Cc: ralf@linux-mips.org
Cc: rth@twiddle.net
Cc: tony.luck@intel.com
Cc: vgupta@synopsys.com
Link: https://lkml.kernel.org/r/20190522132250.26499-12-mark.rutland@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-06-03 12:32:56 +02:00
..
asm-offsets.h
…
asm-prototypes.h
RISC-V: include linux/ftrace.h in asm-prototypes.h
2018-09-24 13:12:27 -07:00
asm.h
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
2017-11-30 10:01:10 -08:00
atomic.h
locking/atomic, riscv: Fix atomic64_sub_if_positive() offset argument
2019-06-03 12:32:56 +02:00
barrier.h
riscv/barrier: Define __smp_{store_release,load_acquire}
2018-04-02 19:59:43 -07:00
bitops.h
RISC-V: __test_and_op_bit_ord should be strongly ordered
2017-11-28 14:04:05 -08:00
bug.h
riscv: Add the support for c.ebreak check in is_valid_bugaddr()
2019-05-16 20:42:12 -07:00
cache.h
…
cacheflush.h
riscv: move flush_icache_{all,mm} to cacheflush.c
2019-05-16 20:42:12 -07:00
cmpxchg.h
riscv/atomic: Strengthen implementations with fences
2018-04-02 19:59:44 -07:00
csr.h
RISC-V: Access CSRs using CSR numbers
2019-05-16 20:42:11 -07:00
current.h
…
delay.h
…
elf.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
2019-05-30 11:26:32 -07:00
fence.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
fixmap.h
RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area
2019-03-28 23:16:04 -07:00
ftrace.h
riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support
2018-04-02 19:59:13 -07:00
futex.h
riscv: remove CONFIG_RISCV_ISA_A
2019-04-25 14:51:10 -07:00
hwcap.h
…
io.h
riscv/mmiowb: Hook up mmwiob() implementation to asm-generic code
2019-04-08 12:00:40 +01:00
irq.h
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
2018-08-13 08:31:31 -07:00
irqflags.h
RISC-V: Access CSRs using CSR numbers
2019-05-16 20:42:11 -07:00
Kbuild
treewide: Add SPDX license identifier - Kbuild
2019-05-30 11:32:33 -07:00
kprobes.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
2019-05-30 11:26:41 -07:00
linkage.h
…
mmiowb.h
riscv/mmiowb: Hook up mmwiob() implementation to asm-generic code
2019-04-08 12:00:40 +01:00
mmu_context.h
riscv: move switch_mm to its own file
2019-05-16 20:42:12 -07:00
mmu.h
RISC-V: Flush I$ when making a dirty page executable
2017-11-30 12:58:25 -08:00
module.h
RISC-V: Support MODULE_SECTIONS mechanism on RV32
2019-01-07 08:19:20 -08:00
page.h
RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS" -> "CONFIG_64BIT"
2019-01-23 12:56:20 -08:00
pci.h
PCI: remove PCI_DMA_BUS_IS_PHYS
2018-05-07 07:15:41 +02:00
perf_event.h
RISC-V: Fix !CONFIG_SMP compilation error
2018-08-13 08:31:32 -07:00
pgalloc.h
mm: treewide: remove unused address argument from pte_alloc functions
2019-01-04 13:13:47 -08:00
pgtable-32.h
…
pgtable-64.h
…
pgtable-bits.h
riscv: Add pte bit to distinguish swap from invalid
2019-02-11 15:24:45 -08:00
pgtable.h
RISC-V: Move setup_bootmem() to mm/init.c
2019-02-21 11:25:49 +05:30
processor.h
riscv: Adjust mmap base address at a third of task size
2019-01-25 10:50:53 -08:00
ptrace.h
riscv: remove duplicate macros from ptrace.h
2019-04-25 14:51:11 -07:00
sbi.h
riscv: fix sbi_remote_sfence_vma{,_asid}.
2019-05-16 20:42:12 -07:00
sifive_l2_cache.h
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
2019-05-16 20:42:13 -07:00
smp.h
RISC-V: Move cpuid to hartid mapping to SMP.
2019-03-04 10:40:38 -08:00
spinlock_types.h
…
spinlock.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
string.h
…
switch_to.h
Auto-detect whether a FPU exists
2018-10-22 17:02:23 -07:00
syscall.h
audit/stable-5.2 PR 20190507
2019-05-07 19:06:04 -07:00
thread_info.h
riscv: turn mm_segment_t into a struct
2019-04-25 14:51:10 -07:00
timex.h
RISC-V: Use define for get_cycles like other architectures
2017-11-30 10:12:21 -08:00
tlb.h
asm-generic/tlb, arch: Provide generic tlb_flush() based on flush_tlb_range()
2019-04-03 10:32:42 +02:00
tlbflush.h
RISC-V: Use Linux logical CPU number instead of hartid
2018-10-22 17:03:37 -07:00
uaccess.h
riscv: remove unreachable big endian code
2019-04-25 14:51:10 -07:00
unistd.h
riscv: define NR_syscalls in unistd.h
2019-01-07 08:22:41 -08:00
vdso.h
RISC-V: Define sys_riscv_flush_icache when SMP=n
2018-08-20 10:55:24 -07:00
word-at-a-time.h
…