Shengjiu Wang 347ecf29a6
ASoC: fsl_xcvr: refine the requested phy clock frequency
As the input phy clock frequency will divided by 2 by default
on i.MX8MP with the implementation of clk-imx8mp-audiomix driver,
So the requested frequency need to be updated.

The relation of phy clock is:
    sai_pll_ref_sel
       sai_pll
          sai_pll_bypass
             sai_pll_out
                sai_pll_out_div2
                   earc_phy_cg

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Link: https://lore.kernel.org/r/1700702093-8008-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-11-23 12:41:46 +00:00
..
2023-10-23 19:38:22 +01:00
2023-10-26 17:02:53 +01:00
2023-10-09 13:13:59 +01:00
2023-11-06 10:57:03 +00:00
2023-11-23 12:41:44 +00:00