Archit Taneja 34d9545b9f drm/msm/dsi: Reset both PHYs before clock operation for dual DSI ...

In case of dual DSI, some registers in PHY1 have been programmed
during PLL0 clock's set_rate. The PHY1 reset called by host1 later
will silently reset those PHY1 registers. This change is to reset
and enable both PHYs before any PLL clock operation.

[Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up
by Archit Taneja <architt@codeaurora.org>]

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

2017-02-06 11:28:45 -05:00

..

phy

drm/msm/dsi: Pass down use case to PHY

2017-02-06 11:28:45 -05:00

pll

drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks

2016-11-02 10:48:09 -04:00

dsi_cfg.c

drm/msm/dsi: Add 8x96 info in dsi_cfg

2017-02-06 11:28:44 -05:00

dsi_cfg.h

drm/msm/dsi: Add 8x96 info in dsi_cfg

2017-02-06 11:28:44 -05:00

dsi_host.c

drm/msm/dsi: Reset both PHYs before clock operation for dual DSI

2017-02-06 11:28:45 -05:00

dsi_manager.c

drm/msm/dsi: Reset both PHYs before clock operation for dual DSI

2017-02-06 11:28:45 -05:00

dsi.c

drm/msm: Construct only one encoder for DSI

2017-02-06 11:28:43 -05:00

dsi.h

drm/msm/dsi: Reset both PHYs before clock operation for dual DSI

2017-02-06 11:28:45 -05:00

dsi.xml.h

drm/msm/dsi: Update generated headers

2017-02-06 11:28:43 -05:00

mmss_cc.xml.h

drm/msm: update generated headers

2016-11-28 15:14:10 -05:00

sfpb.xml.h

drm/msm: update generated headers

2016-11-28 15:14:10 -05:00