761b4f694c
Some CPUs don't support icache specific instructions to flush icache lines in broadcast way. We use cpu control registers to flush local icache and use IPI to notify other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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#include <asm/barrier.h>
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#define INS_CACHE (1 << 0)
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#define CACHE_INV (1 << 4)
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void local_icache_inv_all(void *priv)
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{
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mtcr("cr17", INS_CACHE|CACHE_INV);
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sync_is();
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}
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void icache_inv_all(void)
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{
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on_each_cpu(local_icache_inv_all, NULL, 1);
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}
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#ifdef CONFIG_CPU_HAS_ICACHE_INS
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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#else
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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icache_inv_all();
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}
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#endif
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inline void dcache_wb_line(unsigned long start)
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{
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asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
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sync_is();
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}
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void dcache_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dcache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void cache_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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icache_inv_range(start, end);
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}
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EXPORT_SYMBOL(cache_wbinv_range);
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void dma_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cva %0\n"::"r"(i):"memory");
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sync_is();
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}
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